{"id":"https://openalex.org/W2432817829","doi":"https://doi.org/10.1109/mm.2016.36","title":"Accelerating the Accelerator Memory Interface with Access-Execute and Dataflow","display_name":"Accelerating the Accelerator Memory Interface with Access-Execute and Dataflow","publication_year":2016,"publication_date":"2016-05-01","ids":{"openalex":"https://openalex.org/W2432817829","doi":"https://doi.org/10.1109/mm.2016.36","mag":"2432817829"},"language":"en","primary_location":{"id":"doi:10.1109/mm.2016.36","doi":"https://doi.org/10.1109/mm.2016.36","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mm.2016.36","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","dongbi-a","jufo-3","norway-2","poland-140","russia-white-list-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"},"volume":null,"type":"article","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5032872832","display_name":"Chen-Han Ho","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chen-Han Ho","raw_affiliation_strings":["University of Wisconsin, Madison"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Wisconsin, Madison","institution_ids":["https://openalex.org/I135310074"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113951739","display_name":"Sung Jin Kim","orcid":"https://orcid.org/0000-0003-4469-3024","observed_orcids":["https://orcid.org/0000-0003-4469-3024"]},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sung Jin Kim","raw_affiliation_strings":["University of Wisconsin, Madison"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Wisconsin, Madison","institution_ids":["https://openalex.org/I135310074"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028943049","display_name":"Karthikeyan Sankaralingam","orcid":"https://orcid.org/0000-0002-8315-2389","observed_orcids":["https://orcid.org/0000-0002-8315-2389"]},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Karthikeyan Sankaralingam","raw_affiliation_strings":["University of Wisconsin--Madison"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Wisconsin--Madison","institution_ids":["https://openalex.org/I135310074"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I135310074"],"apc_list":{"value":2995,"currency":"USD","value_usd":2995},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.05427754,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"36","issue":"3","first_page":"31","last_page":"41"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9922000169754028,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9922000169754028,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.006200000178068876,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.0005000000237487257,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/event-condition-action-rules","display_name":"event-condition-action rules","score":0.7789999842643738},{"id":"https://openalex.org/keywords/out-of-order-cores","display_name":"out-of-order cores","score":0.7940000295639038},{"id":"https://openalex.org/keywords/low-power-processor-design","display_name":"low-power processor design","score":0.4830000102519989},{"id":"https://openalex.org/keywords/energy-efficiency","display_name":"energy efficiency","score":0.6489999890327454},{"id":"https://openalex.org/keywords/hardware-architecture","display_name":"hardware architecture","score":0.45500001311302185}],"concepts":[{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.96141117811203},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.9050111770629883},{"id":"https://openalex.org/C176727019","wikidata":"https://www.wikidata.org/wiki/Q1172415","display_name":"Dataflow architecture","level":3,"score":0.6213206052780151},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5103663802146912},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.46068575978279114},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.45714783668518066},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.44996991753578186},{"id":"https://openalex.org/C18131444","wikidata":"https://www.wikidata.org/wiki/Q163585","display_name":"Memory protection","level":5,"score":0.4358534514904022},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4196082353591919},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.41841888427734375},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.37882304191589355},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.23476353287696838},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.1312842071056366},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mm.2016.36","doi":"https://doi.org/10.1109/mm.2016.36","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mm.2016.36","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","dongbi-a","jufo-3","norway-2","poland-140","russia-white-list-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1494460186","https://openalex.org/W1604345466","https://openalex.org/W1966852412","https://openalex.org/W1969529818","https://openalex.org/W1969648707","https://openalex.org/W2035924020","https://openalex.org/W2074812550","https://openalex.org/W2105339504","https://openalex.org/W2125310891","https://openalex.org/W2187230075","https://openalex.org/W4236433846"],"related_works":["https://openalex.org/W4236084225","https://openalex.org/W2898945904","https://openalex.org/W4308083596","https://openalex.org/W4411486154","https://openalex.org/W4244668938","https://openalex.org/W4246642427","https://openalex.org/W7220785326","https://openalex.org/W4242316748","https://openalex.org/W2141064437","https://openalex.org/W4393146147"],"abstract_inverted_index":{"The":[0],"Memory":[1],"Access":[2],"Dataflow":[3],"execution":[4],"model":[5],"and":[6,14,18,83],"hardware":[7],"architecture":[8],"combine":[9],"principles":[10],"of":[11,26],"decoupled":[12],"access":[13],"execution,":[15],"dataflow":[16],"computation,":[17],"event-condition-action":[19],"rules":[20],"to":[21,51,61],"redevelop":[22],"the":[23,78],"main":[24],"primitives":[25],"an":[27,52],"out-of-order":[28],"core":[29,79],"in":[30,41],"a":[31,55],"power-efficient":[32],"way":[33],"that":[34,38],"targets":[35],"memory":[36],"accesses":[37],"naturally":[39],"occur":[40],"programs":[42],"or":[43,65],"get":[44],"induced":[45],"when":[46],"some":[47],"work":[48],"is":[49],"offloaded":[50],"accelerator.":[53],"Such":[54],"mechanism":[56],"can":[57],"allow":[58],"in-core":[59],"accelerators":[60],"integrate":[62],"with":[63],"high-":[64],"low-performance":[66],"cores":[67],"without":[68],"compromising":[69],"performance,":[70],"run":[71],"at":[72],"low":[73],"power":[74],"by":[75],"turning":[76],"off":[77],"during":[80],"such":[81],"phases,":[82],"provide":[84],"high":[85],"energy":[86],"savings.":[87]},"counts_by_year":[],"updated_date":"2026-10-16T09:59:22.235173","created_date":"2016-06-24T00:00:00"}
