{"id":"https://openalex.org/W2399323803","doi":"https://doi.org/10.1109/tcad.2015.2481873","title":"A Zonotoped Macromodeling for Eye-Diagram Verification of High-Speed I/O Links With Jitter and Parameter Variations","display_name":"A Zonotoped Macromodeling for Eye-Diagram Verification of High-Speed I/O Links With Jitter and Parameter Variations","publication_year":2015,"publication_date":"2015-09-24","ids":{"openalex":"https://openalex.org/W2399323803","doi":"https://doi.org/10.1109/tcad.2015.2481873","mag":"2399323803"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2015.2481873","doi":"https://doi.org/10.1109/tcad.2015.2481873","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2015.2481873","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["ccf-a","cwts-core","dongbi-a","jufo-2","norway-1","poland-100","russia-white-list-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"volume":null,"type":"article","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030240223","display_name":"Leibin Ni","orcid":"https://orcid.org/0000-0002-5480-3146","observed_orcids":["https://orcid.org/0000-0002-5480-3146"]},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Leibin Ni","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047725314","display_name":"Sai Manoj Pudukotai Dinakarrao","orcid":"https://orcid.org/0000-0002-4417-2387","observed_orcids":["https://orcid.org/0000-0002-4417-2387"]},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Sai Manoj P. D.","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025482368","display_name":"Yang Song","orcid":"https://orcid.org/0000-0001-9236-4538","observed_orcids":["https://orcid.org/0000-0001-9236-4538"]},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yang Song","raw_affiliation_strings":["School of Electrical and Computer Engineering, University of California, San Diego, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, University of California, San Diego, CA, USA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Chenjie Gu","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chenjie Gu","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100432170","display_name":"Hao Yu","orcid":"https://orcid.org/0000-0001-8747-3203","observed_orcids":["https://orcid.org/0000-0001-8747-3203","https://orcid.org/0009-0000-0752-4251","https://orcid.org/0009-0000-7582-3325"]},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Hao Yu","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":2645,"currency":"USD","value_usd":2645},"apc_paid":null,"fwci":1.1474,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.80202833,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":88,"max":96},"biblio":{"volume":"35","issue":"6","first_page":"1040","last_page":"1051"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.5332000255584717,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.5332000255584717,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.32839998602867126,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.04969999939203262,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/zonotopes","display_name":"zonotopes","score":0.8610000014305115},{"id":"https://openalex.org/keywords/macromodeling","display_name":"macromodeling","score":0.8080000281333923},{"id":"https://openalex.org/keywords/jitter","display_name":"jitter","score":0.8679999709129333},{"id":"https://openalex.org/keywords/parameter-variation","display_name":"parameter variation","score":0.7749999761581421},{"id":"https://openalex.org/keywords/reachability-analysis","display_name":"reachability analysis","score":0.9789999723434448},{"id":"https://openalex.org/keywords/performance-bounds","display_name":"performance bounds","score":0.6579999923706055},{"id":"https://openalex.org/keywords/uncertainty-modeling","display_name":"uncertainty modeling","score":0.6010000109672546},{"id":"https://openalex.org/keywords/analog-circuit-verification","display_name":"analog circuit verification","score":0.5429999828338623}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.8887576460838318},{"id":"https://openalex.org/C186399060","wikidata":"https://www.wikidata.org/wiki/Q959962","display_name":"Diagram","level":2,"score":0.7092156410217285},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4652949571609497},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.35230210423469543},{"id":"https://openalex.org/C120665830","wikidata":"https://www.wikidata.org/wiki/Q14620","display_name":"Optics","level":1,"score":0.3346213102340698},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.13908958435058594},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2015.2481873","doi":"https://doi.org/10.1109/tcad.2015.2481873","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2015.2481873","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["ccf-a","cwts-core","dongbi-a","jufo-2","norway-1","poland-100","russia-white-list-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320307102","display_name":"Intel Corporation","ror":"https://ror.org/01ek73717"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":45,"referenced_works":["https://openalex.org/W1511213320","https://openalex.org/W1569692898","https://openalex.org/W1986324905","https://openalex.org/W2002936353","https://openalex.org/W2005711196","https://openalex.org/W2012621058","https://openalex.org/W2029021634","https://openalex.org/W2052490383","https://openalex.org/W2086022517","https://openalex.org/W2093064288","https://openalex.org/W2103244535","https://openalex.org/W2107001724","https://openalex.org/W2107818375","https://openalex.org/W2111353004","https://openalex.org/W2112436573","https://openalex.org/W2113085759","https://openalex.org/W2122608783","https://openalex.org/W2125853937","https://openalex.org/W2132616434","https://openalex.org/W2140823559","https://openalex.org/W2142091551","https://openalex.org/W2143802986","https://openalex.org/W2145686284","https://openalex.org/W2146641106","https://openalex.org/W2147661346","https://openalex.org/W2154725907","https://openalex.org/W2156717285","https://openalex.org/W2159160377","https://openalex.org/W2162313341","https://openalex.org/W2168901237","https://openalex.org/W2170825877","https://openalex.org/W2172042498","https://openalex.org/W2172429372","https://openalex.org/W2566193534","https://openalex.org/W2750147881","https://openalex.org/W3142232850","https://openalex.org/W3148061895","https://openalex.org/W3148956571","https://openalex.org/W4233824903","https://openalex.org/W4235187868","https://openalex.org/W4237018314","https://openalex.org/W4248748862","https://openalex.org/W4253299980","https://openalex.org/W4255364734","https://openalex.org/W6650932037"],"related_works":["https://openalex.org/W2006898728","https://openalex.org/W2154821452","https://openalex.org/W2060184678","https://openalex.org/W2144514679","https://openalex.org/W2111439418","https://openalex.org/W2079686156","https://openalex.org/W2074486236","https://openalex.org/W7099643924","https://openalex.org/W2101197344","https://openalex.org/W2934151202"],"abstract_inverted_index":{"It":[0],"is":[1,40,70],"challenging":[2],"to":[3,25,45,73,118,122],"efficiently":[4],"evaluate":[5],"the":[6,21,47,75,84,91,96,113,123,128],"performance":[7,101],"bound":[8,79],"of":[9,23,28,127],"high-precision":[10],"analog":[11],"circuits":[12],"with":[13],"input":[14,29],"and":[15,34,59,106],"parameter":[16,85],"variations":[17,61,86],"at":[18],"nano-scale.":[19],"With":[20],"use":[22],"zonotope":[24],"model":[26,130],"uncertainty":[27],"data":[30],"pattern":[31],"(or":[32],"jitter)":[33],"multiple":[35],"parameters,":[36],"a":[37,66],"reachability-based":[38],"verification":[39],"developed":[41,72],"in":[42,62],"this":[43],"paper":[44],"compute":[46],"worst-case":[48],"eye-diagram.":[49],"The":[50],"proposed":[51,97],"zonotope-based":[52],"reachability":[53],"analysis":[54],"can":[55],"consider":[56],"both":[57,104],"spatial":[58,107],"temporal":[60,105],"one-time":[63],"simulation.":[64],"Moreover,":[65],"nonlinear":[67],"zonotoped":[68,98,114],"macromodeling":[69],"further":[71],"reduce":[74],"computational":[76],"complexity.":[77],"Performance":[78],"for":[80,100,138],"I/O":[81,140],"links":[82,141],"considering":[83,103],"are":[87,93],"evaluated.":[88],"In":[89],"addition,":[90],"eye-diagrams":[92],"generated":[94],"by":[95,111],"macromodel":[99,115,136],"evaluation":[102],"variations.":[108],"As":[109],"shown":[110],"experiments,":[112],"achieves":[116],"up":[117],"450\u00d7":[119],"speedup":[120],"compared":[121],"Monte":[124],"Carlo":[125],"simulation":[126],"original":[129],"within":[131],"small":[132],"error":[133],"under":[134],"specified":[135],"order":[137],"high-speed":[139],"eye-diagram":[142],"verification.":[143]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2}],"updated_date":"2026-11-04T10:54:05.112534","created_date":"2016-06-24T00:00:00"}