{"id":"https://openalex.org/W2393658466","doi":null,"title":"Circuit layout design based on thick-film process","display_name":"Circuit layout design based on thick-film process","publication_year":2014,"publication_date":"2014-01-01","ids":{"openalex":"https://openalex.org/W2393658466","mag":"2393658466"},"language":"en","primary_location":{"id":"mag:2393658466","doi":null,"is_oa":false,"landing_page_url":"https://en.cnki.com.cn/Article_en/CJFDTOTAL-XDDJ201404034.htm","pdf_url":null,"source":{"id":"https://openalex.org/S2764664148","display_name":"Modern Electronics Technique","issn_l":"1004-373X","issn":["1004-373X"],"is_oa":false,"is_in_doaj":true,"is_core":false,"listed_in":["doaj"],"host_organization":"https://openalex.org/P4320800568","host_organization_name":"Chinese Institute of Electronics","host_organization_lineage":["https://openalex.org/P4320800568"],"host_organization_lineage_names":["Chinese Institute of Electronics"],"type":"journal"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":"Modern Electronics Technique","raw_type":null},"volume":null,"type":"article","is_traditional":true,"indexed_in":[],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049062134","display_name":"PU Ya-fan","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"PU Ya-fan","raw_affiliation_strings":["Shaanxi HuaJing Microelectronics Co"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Shaanxi HuaJing Microelectronics Co","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":["https://openalex.org/A5049062134"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.0,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10460","display_name":"Electronic Packaging and Soldering Technologies","score":0.6518999934196472,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10460","display_name":"Electronic Packaging and Soldering Technologies","score":0.6518999934196472,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.24120000004768372,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13251","display_name":"Electrical and Thermal Properties of Materials","score":0.04259999841451645,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/circuit-layout-design","display_name":"circuit layout design","score":0.9470000267028809},{"id":"https://openalex.org/keywords/printed-circuit-board-technology","display_name":"printed circuit board technology","score":0.6840000152587891},{"id":"https://openalex.org/keywords/device-encapsulation","display_name":"device encapsulation","score":0.8199999928474426},{"id":"https://openalex.org/keywords/compact-circuit-design","display_name":"compact circuit design","score":0.5460000038146973},{"id":"https://openalex.org/keywords/design-scheme-comparison","display_name":"design scheme comparison","score":0.5329999923706055}],"concepts":[{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.7720534801483154},{"id":"https://openalex.org/C179145894","wikidata":"https://www.wikidata.org/wiki/Q5264353","display_name":"Design layout record","level":5,"score":0.7517389059066772},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.6759787201881409},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.6736522316932678},{"id":"https://openalex.org/C2776378722","wikidata":"https://www.wikidata.org/wiki/Q3454417","display_name":"Realizability","level":2,"score":0.6373919248580933},{"id":"https://openalex.org/C188058453","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Discrete circuit","level":4,"score":0.597091794013977},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5384912490844727},{"id":"https://openalex.org/C120793396","wikidata":"https://www.wikidata.org/wiki/Q173350","display_name":"Printed circuit board","level":2,"score":0.5141963958740234},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4987673759460449},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.46021902561187744},{"id":"https://openalex.org/C188985296","wikidata":"https://www.wikidata.org/wiki/Q868954","display_name":"Page layout","level":2,"score":0.4318923354148865},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.4156903922557831},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4111729860305786},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.37848982214927673},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.36493581533432007},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3030717074871063},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.12598931789398193},{"id":"https://openalex.org/C112698675","wikidata":"https://www.wikidata.org/wiki/Q37038","display_name":"Advertising","level":1,"score":0.0},{"id":"https://openalex.org/C144133560","wikidata":"https://www.wikidata.org/wiki/Q4830453","display_name":"Business","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"mag:2393658466","doi":null,"is_oa":false,"landing_page_url":"https://en.cnki.com.cn/Article_en/CJFDTOTAL-XDDJ201404034.htm","pdf_url":null,"source":{"id":"https://openalex.org/S2764664148","display_name":"Modern Electronics Technique","issn_l":"1004-373X","issn":["1004-373X"],"is_oa":false,"is_in_doaj":true,"is_core":false,"listed_in":["doaj"],"host_organization":"https://openalex.org/P4320800568","host_organization_name":"Chinese Institute of Electronics","host_organization_lineage":["https://openalex.org/P4320800568"],"host_organization_lineage_names":["Chinese Institute of Electronics"],"type":"journal"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":"Modern Electronics Technique","raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5378999710083008,"id":"https://metadata.un.org/sdg/9"}],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2272333852","https://openalex.org/W2235477855","https://openalex.org/W2010539129","https://openalex.org/W3046179272","https://openalex.org/W1834094089","https://openalex.org/W1677758542","https://openalex.org/W6981026158","https://openalex.org/W2269172351","https://openalex.org/W2043715975","https://openalex.org/W2019213302"],"abstract_inverted_index":{"The":[0,37,111,124],"printed":[1],"circuit":[2,8,18,45,57,72,84,105,121,131],"board(PCB)":[3],"technology":[4],"is":[5,13,61],"applied":[6],"to":[7,76],"design":[9,54,73,99,107,133],"generally.":[10],"If":[11],"it":[12],"combined":[14],"with":[15],"thick-film":[16,115],"process,the":[17],"layout":[19,58,109,122,132],"design,in":[20],"which":[21,65],"the":[22,41,62,68,71,77,82,93,98,120,127],"complicated":[23],"connection":[24],"and":[25,86,95,108],"many":[26],"devices":[27],"are":[28],"mounted":[29],"in":[30,119],"its":[31],"limited":[32],"room,":[33],"can":[34,66],"be":[35],"implemented.":[36],"outstanding":[38,112],"advantages":[39],"of":[40,51,56,70,81,97,114],"thick-":[42],"film":[43],"hybrid":[44],"were":[46,90,101],"demonstrated":[47],"by":[48,103],"theoretical":[49],"analysis":[50],"three":[52],"defferent":[53],"schemes":[55],"design.":[59,110,123],"It":[60],"unique":[63],"one":[64],"meet":[67],"requirement":[69,80],"scheme.":[74],"According":[75],"boundary":[78],"dimension":[79],"circuit,the":[83],"performance":[85],"device":[87],"encapsulation":[88],"mode":[89],"considered":[91],"thoroughly,and":[92],"rationality":[94],"realizability":[96],"scheme":[100],"validated":[102],"reasonable":[104],"segmenting":[106],"superiority":[113],"process":[116],"was":[117,137],"reflected":[118],"difficulty":[125],"that":[126],"conventional":[128],"methods":[129],"for":[130],"could":[134],"not":[135],"overcome":[136],"solved":[138],"easily.":[139]},"counts_by_year":[],"updated_date":"2026-07-28T07:46:37.118299","created_date":"2016-06-24T00:00:00"}