{"id":"https://openalex.org/W2392912773","doi":null,"title":"A Dual Charge Pump PLL-based Clock Generator with Power Down Schemes for Low Power Systems","display_name":"A Dual Charge Pump PLL-based Clock Generator with Power Down Schemes for Low Power Systems","publication_year":2005,"publication_date":"2005-01-01","ids":{"openalex":"https://openalex.org/W2392912773","mag":"2392912773"},"language":"en","primary_location":{"id":"mag:2392912773","doi":null,"is_oa":false,"landing_page_url":"https://www.kci.go.kr/kciportal/ci/sereArticleSearch/ciSereArtiView.kci?sereArticleSearchBean.artiId=ART000994017","pdf_url":null,"source":{"id":"https://openalex.org/S2764675581","display_name":"Journal of the Institute of Electronics Engineers of Korea","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":"Journal of the Institute of Electronics Engineers of Korea","raw_type":null},"volume":null,"type":"article","is_traditional":true,"indexed_in":[],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5079267409","display_name":"Jong-Chan Ha","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Jong-Chan Ha","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101752671","display_name":"Taejin Hwang","orcid":"https://orcid.org/0000-0002-7001-9634","observed_orcids":["https://orcid.org/0000-0002-7001-9634"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Taejin Hwang","raw_affiliation_strings":[],"raw_orcid":"https://orcid.org/0000-0002-7001-9634","affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5074950993","display_name":"Jae-Kyung Wee","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Jae-Kyung Wee","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.4590096,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"42","issue":"11","first_page":"695","last_page":"702"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.00019999999494757503,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":9.999999747378752e-05,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"phase-locked loop","score":0.8790000081062317},{"id":"https://openalex.org/keywords/clock-generator","display_name":"clock generator","score":0.9169999957084656},{"id":"https://openalex.org/keywords/low-power-consumption","display_name":"low power consumption","score":0.6320000290870667},{"id":"https://openalex.org/keywords/power-down-mode","display_name":"power-down mode","score":0.7900000214576721},{"id":"https://openalex.org/keywords/programmable-frequency-divider","display_name":"programmable frequency divider","score":0.699999988079071},{"id":"https://openalex.org/keywords/multiple-clock-domains","display_name":"multiple clock domains","score":0.7789999842643738},{"id":"https://openalex.org/keywords/locking-time","display_name":"lock time","score":0.4339999854564667},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5109999775886536}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.8730041980743408},{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.8446133732795715},{"id":"https://openalex.org/C77881186","wikidata":"https://www.wikidata.org/wiki/Q7119642","display_name":"PLL multibit","level":4,"score":0.6231793761253357},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6058111190795898},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5133978128433228},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4915517270565033},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.48246127367019653},{"id":"https://openalex.org/C114825011","wikidata":"https://www.wikidata.org/wiki/Q440704","display_name":"Charge pump","level":4,"score":0.42980679869651794},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.42684996128082275},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.357517808675766},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.3096902370452881},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2934982180595398},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25409194827079773},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.16328105330467224},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.15931448340415955},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.13820293545722961},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09900009632110596},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"mag:2392912773","doi":null,"is_oa":false,"landing_page_url":"https://www.kci.go.kr/kciportal/ci/sereArticleSearch/ciSereArtiView.kci?sereArticleSearchBean.artiId=ART000994017","pdf_url":null,"source":{"id":"https://openalex.org/S2764675581","display_name":"Journal of the Institute of Electronics Engineers of Korea","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/P4320800604","host_organization_name":"Institute of Electronics, Information and Communication Engineers","host_organization_lineage":["https://openalex.org/P4320800604"],"host_organization_lineage_names":["Institute of Electronics, Information and Communication Engineers"],"type":"journal"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":"Journal of the Institute of Electronics Engineers of Korea","raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W1943750926","https://openalex.org/W3153540426","https://openalex.org/W2509603387","https://openalex.org/W1503780886","https://openalex.org/W2175023340","https://openalex.org/W2810353317","https://openalex.org/W1975317045","https://openalex.org/W2138448997","https://openalex.org/W2331764263","https://openalex.org/W2534976622"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"a":[3,13,39,46,55,82,106,120,154,164],"programmable":[4,97,151],"PLL":[5,64,139,149],"(phase":[6],"locked":[7],"loop)":[8],"based":[9],"clock":[10,27,117,161],"generator":[11],"supporting":[12,105],"wide-range-frequency":[14],"input":[15],"and":[16,21,37],"output":[17,98],"for":[18,87,104,159],"high":[19],"performance":[20],"low":[22,51],"power":[23,52,128,140],"SoC":[24],"with":[25,126],"multiple":[26,165],"frequencies":[28],"domains.":[29],"The":[30,96,114],"propose":[31],"system":[32,118],"reduces":[33],"the":[34,57,62,69,73,79,88,148],"locking":[35,58,74,145,156],"time":[36,122],"obtains":[38],"wide":[40,155],"range":[41,123,157],"operation":[42,53,91,109],"frequency":[43,99],"by":[44,78],"using":[45,150],"dual-charge":[47],"pumps":[48],"scheme.":[49],"For":[50],"of":[54,61,124,144],"chip,":[56],"processing":[59],"circuits":[60],"proposed":[63,115],"doesn't":[65],"be":[66],"working":[67],"in":[68],"standby":[70],"mode":[71,94],"but":[72],"data":[75],"are":[76,102],"retained":[77],"DAC.":[80],"Also,":[81,147],"tracking":[83],"ADC":[84],"is":[85,131],"designed":[86,103],"fast":[89],"relocking":[90],"after":[92],"stand-by":[93],"exit.":[95],"selection's":[100],"circuit":[101],"optimized":[107],"DFS":[108],"according":[110],"to":[111],"job":[112],"tasks.":[113],"PLL-based":[116],"has":[119,153],"relock":[121],"(cycle)":[125],"2.3V":[127],"supply,":[129],"which":[130],"fabricated":[132],"on":[133,163],"CMOS":[134],"Process.":[135],"At":[136],"power-down":[137],"mode,":[138],"saves":[141],"more":[142],"than":[143],"mode.":[146],"divider":[152],"()":[158],"various":[160],"domains":[162],"IPs":[166],"system.":[167]},"counts_by_year":[],"updated_date":"2025-10-10T17:16:08.811792","created_date":"2016-06-24T00:00:00"}
