{"id":"https://openalex.org/W2374787370","doi":"https://doi.org/10.3850/9783981537079_0376","title":"Integration of Mixed-signal Components into Virtual Platforms for Holistic Simulation of Smart Systems","display_name":"Integration of Mixed-signal Components into Virtual Platforms for Holistic Simulation of Smart Systems","publication_year":2016,"publication_date":"2016-01-01","ids":{"openalex":"https://openalex.org/W2374787370","doi":"https://doi.org/10.3850/9783981537079_0376","mag":"2374787370"},"language":"en","primary_location":{"id":"doi:10.3850/9783981537079_0376","doi":"https://doi.org/10.3850/9783981537079_0376","is_oa":false,"landing_page_url":"https://doi.org/10.3850/9783981537079_0376","pdf_url":null,"source":{"id":"https://openalex.org/S4306418181","display_name":"Design, Automation, and Test in Europe","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://iris.polito.it/bitstream/11583/2622804/1/main.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5068919830","display_name":"Enrico Fraccaroli","orcid":"https://orcid.org/0000-0002-9739-6501","observed_orcids":["https://orcid.org/0000-0002-9739-6501"]},"institutions":[{"id":"https://openalex.org/I119439378","display_name":"University of Verona","ror":"https://ror.org/039bp8j42","country_code":"IT","type":"education","lineage":["https://openalex.org/I119439378"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Enrico Fraccaroli","raw_affiliation_strings":["Department of Computer Science, University of Verona, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Verona, Italy","institution_ids":["https://openalex.org/I119439378"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069672683","display_name":"Michele Lora","orcid":"https://orcid.org/0000-0002-6224-4313","observed_orcids":["https://orcid.org/0000-0002-6224-4313"]},"institutions":[{"id":"https://openalex.org/I119439378","display_name":"University of Verona","ror":"https://ror.org/039bp8j42","country_code":"IT","type":"education","lineage":["https://openalex.org/I119439378"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Michele Lora","raw_affiliation_strings":["Department of Computer Science, University of Verona, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Verona, Italy","institution_ids":["https://openalex.org/I119439378"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070652829","display_name":"Sara Vinco","orcid":"https://orcid.org/0000-0001-9666-5194","observed_orcids":["https://orcid.org/0000-0001-9666-5194"]},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Sara Vinco","raw_affiliation_strings":["Department of Computer Engineering, Politecnico di Torino, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Politecnico di Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050479727","display_name":"Davide Quaglia","orcid":"https://orcid.org/0000-0002-0775-939X","observed_orcids":["https://orcid.org/0000-0002-0775-939X"]},"institutions":[{"id":"https://openalex.org/I119439378","display_name":"University of Verona","ror":"https://ror.org/039bp8j42","country_code":"IT","type":"education","lineage":["https://openalex.org/I119439378"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Davide Quaglia","raw_affiliation_strings":["Department of Computer Science, University of Verona, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Verona, Italy","institution_ids":["https://openalex.org/I119439378"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040302302","display_name":"Franco Fummi","orcid":"https://orcid.org/0000-0002-4404-5791","observed_orcids":["https://orcid.org/0000-0002-4404-5791"]},"institutions":[{"id":"https://openalex.org/I119439378","display_name":"University of Verona","ror":"https://ror.org/039bp8j42","country_code":"IT","type":"education","lineage":["https://openalex.org/I119439378"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Franco Fummi","raw_affiliation_strings":["Department of Computer Science, University of Verona, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Verona, Italy","institution_ids":["https://openalex.org/I119439378"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.054,"has_fulltext":true,"cited_by_count":12,"citation_normalized_percentile":{"value":0.86827458,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":93,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1586","last_page":"1591"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.8812999725341797,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.8812999725341797,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13286","display_name":"Modeling and Simulation Systems","score":0.0925000011920929,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.007400000002235174,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mixed-signal-simulation","display_name":"mixed-signal simulation","score":0.8140000104904175},{"id":"https://openalex.org/keywords/virtual-platforms","display_name":"virtual platforms","score":0.9520000219345093},{"id":"https://openalex.org/keywords/verilog-ams","display_name":"Verilog-AMS","score":0.925000011920929},{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.9229999780654907},{"id":"https://openalex.org/keywords/c-integration","display_name":"C++ integration","score":0.43799999356269836},{"id":"https://openalex.org/keywords/model-abstraction","display_name":"model abstraction","score":0.8429999947547913},{"id":"https://openalex.org/keywords/simulation-acceleration","display_name":"simulation acceleration","score":0.7730000019073486},{"id":"https://openalex.org/keywords/co-simulation","display_name":"co-simulation","score":0.7870000004768372},{"id":"https://openalex.org/keywords/intelligent-systems","display_name":"intelligent systems","score":0.6909999847412109},{"id":"https://openalex.org/keywords/hardware-description-languages","display_name":"hardware description languages","score":0.8379999995231628}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7855628728866577},{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.6920996308326721},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.6751574873924255},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.6061267256736755},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.5789073705673218},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5255205631256104},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5044180154800415},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.48043060302734375},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4772638976573944},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.4771242141723633},{"id":"https://openalex.org/C2781207095","wikidata":"https://www.wikidata.org/wiki/Q24963836","display_name":"System-level simulation","level":2,"score":0.450533390045166},{"id":"https://openalex.org/C2780991453","wikidata":"https://www.wikidata.org/wiki/Q3408177","display_name":"Virtual prototyping","level":2,"score":0.446646511554718},{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.41248926520347595},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.34873998165130615},{"id":"https://openalex.org/C44154836","wikidata":"https://www.wikidata.org/wiki/Q45045","display_name":"Simulation","level":1,"score":0.193078875541687},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.18257033824920654},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.1596028208732605},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.157619446516037},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.12596771121025085},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10579392313957214},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.3850/9783981537079_0376","doi":"https://doi.org/10.3850/9783981537079_0376","is_oa":false,"landing_page_url":"https://doi.org/10.3850/9783981537079_0376","pdf_url":null,"source":{"id":"https://openalex.org/S4306418181","display_name":"Design, Automation, and Test in Europe","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","raw_type":"proceedings-article"},{"id":"pmh:oai:porto.polito.it:2622804","doi":null,"is_oa":true,"landing_page_url":"http://porto.polito.it/2622804/","pdf_url":"https://iris.polito.it/bitstream/11583/2622804/1/main.pdf","source":{"id":"https://openalex.org/S4306402038","display_name":"PORTO Publications Open Repository TOrino (Politecnico di Torino)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I177477856","host_organization_name":"Politecnico di Torino","host_organization_lineage":["https://openalex.org/I177477856"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:oai:iris.polito.it:11583/2622804","doi":null,"is_oa":true,"landing_page_url":"http://hdl.handle.net/11583/2622804","pdf_url":null,"source":{"id":"https://openalex.org/S7407055329","display_name":"PORTO@Iris","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"pmh:oai:porto.polito.it:2622804","doi":null,"is_oa":true,"landing_page_url":"http://porto.polito.it/2622804/","pdf_url":"https://iris.polito.it/bitstream/11583/2622804/1/main.pdf","source":{"id":"https://openalex.org/S4306402038","display_name":"PORTO Publications Open Repository TOrino (Politecnico di Torino)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I177477856","host_organization_name":"Politecnico di Torino","host_organization_lineage":["https://openalex.org/I177477856"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"},"sustainable_development_goals":[{"score":0.651199996471405,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2374787370.pdf","grobid_xml":"https://content.openalex.org/works/W2374787370.grobid-xml"},"referenced_works_count":10,"referenced_works":["https://openalex.org/W1581020795","https://openalex.org/W2013523126","https://openalex.org/W2036492779","https://openalex.org/W2086376934","https://openalex.org/W2099629311","https://openalex.org/W2104520397","https://openalex.org/W2123610036","https://openalex.org/W2128857090","https://openalex.org/W2167297942","https://openalex.org/W2169621739"],"related_works":["https://openalex.org/W2616765985","https://openalex.org/W2588628414","https://openalex.org/W3003860940","https://openalex.org/W2613094640","https://openalex.org/W1645067881","https://openalex.org/W2534302980","https://openalex.org/W2126848821","https://openalex.org/W2539742022","https://openalex.org/W2433013732","https://openalex.org/W2013523126"],"abstract_inverted_index":{"Nowadays,":[0],"the":[1,10,40,52,60,72,83,91,101,118],"design":[2],"of":[3,13,24,42,63,74,86,93,120],"applications":[4],"based":[5],"on":[6],"smart":[7],"systems":[8],"requires":[9],"joint":[11],"simulation":[12,95],"both":[14],"digital":[15,46],"and":[16,54,81,117],"analog":[17,64,87,107],"aspects.":[18],"Even":[19],"if":[20],"analog-mixed-signal":[21],"(AMS)":[22],"extensions":[23],"hardware":[25],"description":[26],"languages":[27],"are":[28],"an":[29],"enabling":[30],"factor,":[31],"they":[32],"do":[33],"not":[34],"provide":[35],"a":[36],"general":[37],"methodology":[38],"for":[39],"integration":[41],"AMS":[43],"models":[44,65],"into":[45],"virtual":[47,78,102],"platforms.":[48],"This":[49],"paper":[50],"defines":[51],"problem":[53],"provides":[55],"two":[56],"main":[57],"contributions:":[58],"1)":[59],"automatic":[61,84],"conversion":[62],"from":[66],"Verilog-AMS":[67],"to":[68,70,123],"C++/SystemC,":[69],"remove":[71],"overhead":[73],"co-simulation":[75,114],"with":[76,90,104,115],"traditional":[77],"platform":[79,103],"tools,":[80],"2)":[82],"abstraction":[85,124],"conservative":[88],"models,":[89],"goal":[92],"increasing":[94],"speed.":[96],"Experimental":[97],"results":[98],"show":[99],"that":[100],"automatically":[105],"integrated":[106],"components":[108],"is":[109,125],"40":[110],"times":[111],"faster":[112],"than":[113,127],"Verilog-AMS,":[116],"increase":[119],"speed":[121],"due":[122],"more":[126],"100%.":[128]},"counts_by_year":[{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":2}],"updated_date":"2026-10-05T09:50:58.205359","created_date":"2016-06-24T00:00:00"}