{"id":"https://openalex.org/W2314301201","doi":"https://doi.org/10.1016/j.procs.2016.03.074","title":"8-Bit 250-MS/s ADC Based on SAR Architecture with Novel Comparator at 70 nm Technology Node","display_name":"8-Bit 250-MS/s ADC Based on SAR Architecture with Novel Comparator at 70 nm Technology Node","publication_year":2016,"publication_date":"2016-01-01","ids":{"openalex":"https://openalex.org/W2314301201","doi":"https://doi.org/10.1016/j.procs.2016.03.074","mag":"2314301201"},"language":"en","primary_location":{"id":"doi:10.1016/j.procs.2016.03.074","doi":"https://doi.org/10.1016/j.procs.2016.03.074","is_oa":true,"landing_page_url":"https://doi.org/10.1016/j.procs.2016.03.074","pdf_url":"https://www.sciencedirect.com/science/article/pii/S1877050916002052/pdf","source":{"id":"https://openalex.org/S120348307","display_name":"Procedia Computer Science","issn_l":"1877-0509","issn":["1877-0509"],"is_oa":true,"is_in_doaj":false,"is_core":true,"listed_in":["anvur-scientific","cwts-core","jufo-1","norway-1"],"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Procedia Computer Science","raw_type":"journal-article"},"parent_works":[],"lineage":["https://openalex.org/W2314301201"],"child_works_count":0,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"diamond","oa_url":"https://www.sciencedirect.com/science/article/pii/S1877050916002052/pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5044083563","display_name":"Shreeniwas Daulatabad","orcid":"https://orcid.org/0000-0001-8647-0801","observed_orcids":["https://orcid.org/0000-0001-8647-0801"]},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Shreeniwas Daulatabad","raw_affiliation_strings":["Electrical Engineering Department, Indian Institute of Technology, Bombay 400076, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, Indian Institute of Technology, Bombay 400076, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063975084","display_name":"Vaibhav Neema","orcid":"https://orcid.org/0000-0003-0922-373X","observed_orcids":["https://orcid.org/0000-0003-0922-373X"]},"institutions":[{"id":"https://openalex.org/I138272832","display_name":"Devi Ahilya Vishwavidyalaya","ror":"https://ror.org/05c2p1f98","country_code":"IN","type":"education","lineage":["https://openalex.org/I138272832"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Vaibhav Neema","raw_affiliation_strings":["Electronics & Telecommunication Engineering Department, IET-Devi Ahilya University, Indore 452017, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronics & Telecommunication Engineering Department, IET-Devi Ahilya University, Indore 452017, India","institution_ids":["https://openalex.org/I138272832"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035985978","display_name":"Ambika Prasad Shah","orcid":"https://orcid.org/0000-0003-0810-814X","observed_orcids":["https://orcid.org/0000-0003-0810-814X"]},"institutions":[{"id":"https://openalex.org/I138272832","display_name":"Devi Ahilya Vishwavidyalaya","ror":"https://ror.org/05c2p1f98","country_code":"IN","type":"education","lineage":["https://openalex.org/I138272832"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Ambika Prasad Shah","raw_affiliation_strings":["Electronics & Telecommunication Engineering Department, IET-Devi Ahilya University, Indore 452017, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronics & Telecommunication Engineering Department, IET-Devi Ahilya University, Indore 452017, India","institution_ids":["https://openalex.org/I138272832"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102244118","display_name":"Praveen Singh","orcid":"https://orcid.org/0000-0002-5034-2194","observed_orcids":["https://orcid.org/0000-0002-5034-2194"]},"institutions":[{"id":"https://openalex.org/I138272832","display_name":"Devi Ahilya Vishwavidyalaya","ror":"https://ror.org/05c2p1f98","country_code":"IN","type":"education","lineage":["https://openalex.org/I138272832"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Praveen Singh","raw_affiliation_strings":["Electronics & Telecommunication Engineering Department, IET-Devi Ahilya University, Indore 452017, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronics & Telecommunication Engineering Department, IET-Devi Ahilya University, Indore 452017, India","institution_ids":["https://openalex.org/I138272832"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5063975084"],"corresponding_institution_ids":["https://openalex.org/I138272832"],"apc_list":null,"apc_paid":null,"fwci":1.3951,"has_fulltext":true,"cited_by_count":11,"citation_normalized_percentile":{"value":0.74815359,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":87,"max":96},"biblio":{"volume":"79","issue":null,"first_page":"589","last_page":"596"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.00019999999494757503,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/successive-approximation-register-adc","display_name":"successive approximation register ADC","score":0.9789999723434448},{"id":"https://openalex.org/keywords/analog-to-digital-converter","display_name":"analog-to-digital converter","score":0.9380000233650208},{"id":"https://openalex.org/keywords/comparator-design","display_name":"comparator design","score":0.9240000247955322},{"id":"https://openalex.org/keywords/double-tail-comparator","display_name":"double-tail comparator","score":0.921999990940094},{"id":"https://openalex.org/keywords/low-power-design","display_name":"low power design","score":0.6240000128746033},{"id":"https://openalex.org/keywords/8-bit-adc","display_name":"8-bit ADC","score":0.6890000104904175},{"id":"https://openalex.org/keywords/ring-counter","display_name":"ring counter","score":0.7710000276565552},{"id":"https://openalex.org/keywords/sr-latch","display_name":"SR latch","score":0.7099999785423279},{"id":"https://openalex.org/keywords/in-band-linearity","display_name":"in-band linearity","score":0.5109999775886536}],"concepts":[{"id":"https://openalex.org/C155745195","wikidata":"https://www.wikidata.org/wiki/Q1164179","display_name":"Comparator","level":3,"score":0.952301561832428},{"id":"https://openalex.org/C60154766","wikidata":"https://www.wikidata.org/wiki/Q2650458","display_name":"Successive approximation ADC","level":4,"score":0.8578358888626099},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7151095271110535},{"id":"https://openalex.org/C4305246","wikidata":"https://www.wikidata.org/wiki/Q3885225","display_name":"Least significant bit","level":2,"score":0.6677120327949524},{"id":"https://openalex.org/C2777271169","wikidata":"https://www.wikidata.org/wiki/Q190169","display_name":"Analog-to-digital converter","level":3,"score":0.538227915763855},{"id":"https://openalex.org/C2778422915","wikidata":"https://www.wikidata.org/wiki/Q10302051","display_name":"Converters","level":3,"score":0.5136996507644653},{"id":"https://openalex.org/C2779879419","wikidata":"https://www.wikidata.org/wiki/Q210863","display_name":"Digital-to-analog converter","level":3,"score":0.5026404857635498},{"id":"https://openalex.org/C206565188","wikidata":"https://www.wikidata.org/wiki/Q836482","display_name":"Sample and hold","level":3,"score":0.4685904383659363},{"id":"https://openalex.org/C187919765","wikidata":"https://www.wikidata.org/wiki/Q270159","display_name":"8-bit","level":2,"score":0.42809075117111206},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.42378169298171997},{"id":"https://openalex.org/C71217194","wikidata":"https://www.wikidata.org/wiki/Q575958","display_name":"Differential nonlinearity","level":3,"score":0.4219074249267578},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4134126305580139},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.40826523303985596},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4021965265274048},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.3575156033039093},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2770959436893463},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09264412522315979},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/j.procs.2016.03.074","doi":"https://doi.org/10.1016/j.procs.2016.03.074","is_oa":true,"landing_page_url":"https://doi.org/10.1016/j.procs.2016.03.074","pdf_url":"https://www.sciencedirect.com/science/article/pii/S1877050916002052/pdf","source":{"id":"https://openalex.org/S120348307","display_name":"Procedia Computer Science","issn_l":"1877-0509","issn":["1877-0509"],"is_oa":true,"is_in_doaj":false,"is_core":true,"listed_in":["anvur-scientific","cwts-core","jufo-1","norway-1"],"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Procedia Computer Science","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1016/j.procs.2016.03.074","doi":"https://doi.org/10.1016/j.procs.2016.03.074","is_oa":true,"landing_page_url":"https://doi.org/10.1016/j.procs.2016.03.074","pdf_url":"https://www.sciencedirect.com/science/article/pii/S1877050916002052/pdf","source":{"id":"https://openalex.org/S120348307","display_name":"Procedia Computer Science","issn_l":"1877-0509","issn":["1877-0509"],"is_oa":true,"is_in_doaj":false,"is_core":true,"listed_in":["anvur-scientific","cwts-core","jufo-1","norway-1"],"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Procedia Computer Science","raw_type":"journal-article"},"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2314301201.pdf","grobid_xml":"https://content.openalex.org/works/W2314301201.grobid-xml"},"referenced_works_count":11,"referenced_works":["https://openalex.org/W1968632892","https://openalex.org/W1970246608","https://openalex.org/W2011961048","https://openalex.org/W2050787461","https://openalex.org/W2071060149","https://openalex.org/W2090833324","https://openalex.org/W2108152823","https://openalex.org/W2161345192","https://openalex.org/W2169384616","https://openalex.org/W2187548090","https://openalex.org/W2485074668"],"related_works":["https://openalex.org/W2065761117","https://openalex.org/W4399338438","https://openalex.org/W2772504378","https://openalex.org/W4283822773","https://openalex.org/W4391182916","https://openalex.org/W7131134788","https://openalex.org/W4415757364","https://openalex.org/W4415033889","https://openalex.org/W4319430834","https://openalex.org/W4394940622"],"abstract_inverted_index":{"The":[0,71,86,123],"data":[1],"converters":[2],"are":[3,91],"prerequisite":[4],"for":[5,15,39],"digital":[6],"processing":[7],"of":[8,104,114],"analog":[9],"signals.":[10],"SAR":[11],"ADC":[12,118],"is":[13,73],"preferred":[14],"their":[16],"good":[17],"balance":[18],"between":[19],"speed,":[20],"area":[21],"and":[22,66,89,96,111,133],"power":[23,132],"considerations.":[24],"In":[25],"this":[26],"paper,":[27],"we":[28],"proposed":[29,68,127],"a":[30,54,67],"novel":[31,69],"comparator":[32,128],"design":[33],"based":[34],"on":[35],"double":[36],"tail":[37],"architecture":[38],"an":[40],"8-bit":[41],"successive":[42],"approximation":[43],"register":[44],"analog-to-digital":[45,51,124],"converter.":[46],"We":[47],"implemented":[48],"8":[49],"bit":[50],"converter":[52,125],"contains":[53],"Successive":[55],"Approximation":[56],"register,":[57],"Ring":[58],"counter,":[59],"SR-Latch,":[60],"R2R":[61],"Ladder":[62],"type":[63],"digital-to-analog":[64],"convertor":[65],"comparator.":[70],"circuit":[72],"simulated":[74],"using":[75,82,126],"Predictive":[76],"Technology":[77,81],"model":[78],"70":[79],"nm":[80],"Tanner":[83],"EDA":[84],"tool.":[85],"average":[87],"INL":[88],"DNL":[90],"less":[92,131],"than":[93],"1":[94,97],"LSB":[95],"LSB,":[98],"respectively.":[99],"At":[100],"the":[101,117],"sample":[102],"rate":[103],"250":[105],"MHz":[106],"(2":[107],"GHz":[108],"clock":[109],"Freq)":[110],"supply":[112],"voltage":[113],"1.2":[115],"V,":[116],"consumed":[119],"about":[120],"1.3":[121],"mW.":[122],"deign":[129],"consumes":[130],"thus":[134],"can":[135],"be":[136],"used":[137],"in":[138],"portable":[139],"device.":[140]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":2}],"updated_date":"2026-11-07T11:25:07.637180","created_date":"2016-06-24T00:00:00"}