{"id":"https://openalex.org/W2276007231","doi":null,"title":"Oscillation Test Methodology for Built-In Analog Circuits","display_name":"Oscillation Test Methodology for Built-In Analog Circuits","publication_year":2012,"publication_date":"2012-01-01","ids":{"openalex":"https://openalex.org/W2276007231","mag":"2276007231"},"language":"en","primary_location":{"id":"pmh:oai:CiteSeerX.psu:10.1.1.412.2537","doi":null,"is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.412.2537","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ijceronline.com/papers/Vol2_issue3/AO023868877.pdf","raw_type":"text"},"volume":null,"type":"article","is_traditional":true,"indexed_in":[],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5034177811","display_name":"Sankari","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Sankari","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5087366460","display_name":"P. Sathish Kumar","orcid":"https://orcid.org/0000-0003-1208-1285","observed_orcids":["https://orcid.org/0000-0003-1208-1285"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"P Sathish Kumar","raw_affiliation_strings":[],"raw_orcid":"https://orcid.org/0000-0003-1208-1285","affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.7874,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.74140985,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":88,"max":95},"biblio":{"volume":"2","issue":"3","first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"built-in self-test","score":0.9039999842643738},{"id":"https://openalex.org/keywords/analog-circuit-testing","display_name":"analog circuit testing","score":0.7350000143051147},{"id":"https://openalex.org/keywords/mixed-signal-circuits","display_name":"mixed-signal circuits","score":0.9900000095367432},{"id":"https://openalex.org/keywords/fault-detection","display_name":"fault detection","score":0.6579999923706055},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"fault coverage","score":0.8450000286102295},{"id":"https://openalex.org/keywords/design-for-testability","display_name":"design for testability","score":0.8939999938011169},{"id":"https://openalex.org/keywords/system-on-chip","display_name":"system-on-chip","score":0.7889999747276306}],"concepts":[{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.7695033550262451},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.6910429000854492},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.59999680519104},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5800584554672241},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.565544068813324},{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.5431912541389465},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5262647867202759},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.4765630066394806},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.45065614581108093},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.4448294937610626},{"id":"https://openalex.org/C206565188","wikidata":"https://www.wikidata.org/wiki/Q836482","display_name":"Sample and hold","level":3,"score":0.4362805187702179},{"id":"https://openalex.org/C2778439541","wikidata":"https://www.wikidata.org/wiki/Q7106412","display_name":"Oscillation (cell signaling)","level":2,"score":0.41985005140304565},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.41874101758003235},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3013688921928406},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.25141018629074097},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.22915226221084595},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C54355233","wikidata":"https://www.wikidata.org/wiki/Q7162","display_name":"Genetics","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"pmh:oai:CiteSeerX.psu:10.1.1.412.2537","doi":null,"is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.412.2537","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ijceronline.com/papers/Vol2_issue3/AO023868877.pdf","raw_type":"text"},{"id":"mag:2276007231","doi":null,"is_oa":false,"landing_page_url":"http://www.ijceronline.com/papers/Vol2_issue3/AO023868877.pdf","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2142590167","https://openalex.org/W2151874577"],"related_works":["https://openalex.org/W7100696456","https://openalex.org/W2151874577","https://openalex.org/W2133038126","https://openalex.org/W2158977975","https://openalex.org/W2187825401","https://openalex.org/W112366330","https://openalex.org/W2739075370","https://openalex.org/W2162281676","https://openalex.org/W2156960698","https://openalex.org/W1909129617"],"abstract_inverted_index":{"This":[0],"article":[1],"aims":[2],"to":[3,13,21,25,83,91,95,123],"describe":[4],"the":[5,15,27,56,78,96,100,121,125],"fundamentals":[6],"of":[7,17,55,99,120],"analog":[8,18,28,43,134],"and":[9,20,69,116],"digital":[10,85,97],"testing":[11,19,42],"methods":[12],"analyze":[14],"difficulties":[16],"develop":[22],"an":[23],"approach":[24],"test":[26,70,92,103,149],"components":[29,44],"in":[30,45,48,109,112,139],"a":[31],"mixed":[32,113],"signal":[33,114],"circuit":[34,101],"environment.":[35],"Oscillation":[36,151],"based,":[37],"built-in":[38,147,153],"self-test":[39],"methodology":[40],"for":[41,160],"mixed-signal":[46],"circuits,":[47],"particular,":[49],"is":[50,59,81],"discussed.":[51],"A":[52],"major":[53],"advantage":[54],"OBIST":[57,105],"method":[58],"that":[60],"it":[61,86],"does":[62],"not":[63],"require":[64],"any":[65],"complex":[66],"response":[67],"analyzers":[68],"vector":[71],"generators":[72],"which":[73],"are":[74,137],"costly":[75],"Furthermore,":[76],"since":[77],"oscillation":[79],"frequency":[80],"considered":[82],"be":[84,88],"can":[87],"easily":[89],"interfaced":[90],"techniques":[93,106],"dedicated":[94],"part":[98],"under":[102],"(CUT).":[104],"show":[107],"promise":[108],"detecting":[110],"faults":[111],"circuits":[115,136],"requires":[117],"little":[118],"modification":[119],"CUT":[122],"improve":[124],"fault":[126],"coverage.":[127],"Extensive":[128],"simulation":[129],"results":[130],"on":[131,144],"some":[132],"sample":[133],"benchmark":[135],"described":[138],"Spice":[140],"format.":[141],"Keywords-":[142],"System":[143],"chip":[145],"(SOC),":[146],"Self":[148],"(BIST),":[150],"based":[152],"self":[154],"test(OBIST),":[155],"Circuit":[156],"Under":[157],"Test(CUT),":[158],"Design":[159],"Testabiltity":[161],"(DFT).":[162]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2015,"cited_by_count":2}],"updated_date":"2026-11-08T12:12:28.789561","created_date":"2016-06-24T00:00:00"}