{"id":"https://openalex.org/W227380729","doi":"https://doi.org/10.1016/b978-0-12-417137-4.00002-2","title":"Multicore and parallel program design","display_name":"Multicore and parallel program design","publication_year":2015,"publication_date":"2015-01-01","ids":{"openalex":"https://openalex.org/W227380729","doi":"https://doi.org/10.1016/b978-0-12-417137-4.00002-2","mag":"227380729"},"language":"en","primary_location":{"id":"doi:10.1016/b978-0-12-417137-4.00002-2","doi":"https://doi.org/10.1016/b978-0-12-417137-4.00002-2","is_oa":false,"landing_page_url":"https://doi.org/10.1016/b978-0-12-417137-4.00002-2","pdf_url":null,"source":{"id":"https://openalex.org/S4306463230","display_name":"Elsevier eBooks","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"ebook platform"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Multicore and GPU Programming","raw_type":"book-chapter"},"volume":{"id":"https://openalex.org/W4250040949","display_name":"Multicore and GPU Programming"},"type":"book-chapter","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5042753036","display_name":"Gerassimos Barlas","orcid":"https://orcid.org/0000-0002-9792-9638","observed_orcids":["https://orcid.org/0000-0002-9792-9638"]},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Gerassimos Barlas","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":["https://openalex.org/A5042753036"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.0,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":88,"max":93},"biblio":{"volume":null,"issue":null,"first_page":"27","last_page":"54"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9818999767303467,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9818999767303467,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.010400000028312206,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.0010999999940395355,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multicore-programming","display_name":"multicore programming","score":0.8199999928474426},{"id":"https://openalex.org/keywords/parallel-program-design","display_name":"parallel program design","score":0.9509999752044678},{"id":"https://openalex.org/keywords/workload-partitioning","display_name":"workload partitioning","score":0.7720000147819519},{"id":"https://openalex.org/keywords/task-mapping","display_name":"task mapping","score":0.7009999752044678},{"id":"https://openalex.org/keywords/decomposition-patterns","display_name":"decomposition patterns","score":0.8519999980926514},{"id":"https://openalex.org/keywords/mapreduce","display_name":"MapReduce","score":0.8220000267028809}],"concepts":[{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.6108985543251038},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5691306591033936},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5298927426338196},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35143476724624634}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/b978-0-12-417137-4.00002-2","doi":"https://doi.org/10.1016/b978-0-12-417137-4.00002-2","is_oa":false,"landing_page_url":"https://doi.org/10.1016/b978-0-12-417137-4.00002-2","pdf_url":null,"source":{"id":"https://openalex.org/S4306463230","display_name":"Elsevier eBooks","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"ebook platform"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Multicore and GPU Programming","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1578415644","https://openalex.org/W2149236087","https://openalex.org/W2155815531","https://openalex.org/W2302914195"],"related_works":["https://openalex.org/W7060737823","https://openalex.org/W3148057506","https://openalex.org/W1972955159","https://openalex.org/W4240605289","https://openalex.org/W1607699646","https://openalex.org/W2036348494","https://openalex.org/W2315134722","https://openalex.org/W7056793516","https://openalex.org/W7099076550","https://openalex.org/W2019453274"],"abstract_inverted_index":null,"counts_by_year":[{"year":2022,"cited_by_count":1}],"updated_date":"2026-10-10T09:11:00.788812","created_date":"2016-06-24T00:00:00"}
