{"id":"https://openalex.org/W2183177152","doi":null,"title":"Design:USB 1.1 SIE (Serial Interface Engine) Transmitter using VHDL","display_name":"Design:USB 1.1 SIE (Serial Interface Engine) Transmitter using VHDL","publication_year":2011,"publication_date":"2011-01-01","ids":{"openalex":"https://openalex.org/W2183177152","mag":"2183177152"},"language":"de","primary_location":{"id":"mag:2183177152","doi":null,"is_oa":false,"landing_page_url":"http://ijcst.com/vol24/3/asutosh.pdf","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":null},"volume":null,"type":"article","is_traditional":true,"indexed_in":[],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Asutosh Das","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Asutosh Das","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047593933","display_name":"Swikriti Thakur","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Swikriti Thakur","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057829814","display_name":"Soumya Mishra","orcid":"https://orcid.org/0000-0003-4773-1727","observed_orcids":["https://orcid.org/0000-0003-4773-1727"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Soumya Mishra","raw_affiliation_strings":[],"raw_orcid":"https://orcid.org/0000-0003-4773-1727","affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015786901","display_name":"Vipul Ingle","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Vipul Ingle","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5001134816","display_name":"Pradeep Kumar Jaisal","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Pradeep Kumar Jaisal","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.0,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12941","display_name":"Embedded Systems and FPGA Design","score":0.0,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/usb-1-1","display_name":"USB 1.1","score":0.9959999918937683},{"id":"https://openalex.org/keywords/transmitter","display_name":"transmitter","score":0.5960000157356262},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.7409999966621399},{"id":"https://openalex.org/keywords/low-speed-data-transmission","display_name":"low-speed data transmission","score":0.996999979019165},{"id":"https://openalex.org/keywords/behavioral-modeling","display_name":"behavioral modeling","score":0.6949999928474426}],"concepts":[{"id":"https://openalex.org/C507366226","wikidata":"https://www.wikidata.org/wiki/Q42378","display_name":"USB","level":3,"score":0.9598500728607178},{"id":"https://openalex.org/C71784007","wikidata":"https://www.wikidata.org/wiki/Q5324733","display_name":"eXtensible Host Controller Interface (xHCI)","level":5,"score":0.8077728748321533},{"id":"https://openalex.org/C37360884","wikidata":"https://www.wikidata.org/wiki/Q13551889","display_name":"Host controller interface","level":5,"score":0.7740964889526367},{"id":"https://openalex.org/C61361435","wikidata":"https://www.wikidata.org/wiki/Q850053","display_name":"USB hub","level":4,"score":0.7269892692565918},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.6974974274635315},{"id":"https://openalex.org/C68160299","wikidata":"https://www.wikidata.org/wiki/Q932506","display_name":"PC Card","level":4,"score":0.6734979152679443},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.6720749139785767},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6600677371025085},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.6428797245025635},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6326106786727905},{"id":"https://openalex.org/C41918916","wikidata":"https://www.wikidata.org/wiki/Q192727","display_name":"PHY","level":4,"score":0.5348426699638367},{"id":"https://openalex.org/C102349902","wikidata":"https://www.wikidata.org/wiki/Q385390","display_name":"Serial port","level":3,"score":0.46450966596603394},{"id":"https://openalex.org/C51707140","wikidata":"https://www.wikidata.org/wiki/Q518280","display_name":"Serial communication","level":2,"score":0.43329310417175293},{"id":"https://openalex.org/C7720470","wikidata":"https://www.wikidata.org/wiki/Q954187","display_name":"Transceiver","level":3,"score":0.4286682605743408},{"id":"https://openalex.org/C557945733","wikidata":"https://www.wikidata.org/wiki/Q389772","display_name":"Data transmission","level":2,"score":0.41944706439971924},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.28550654649734497},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.2268955409526825},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.13302987813949585},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.10566604137420654},{"id":"https://openalex.org/C19247436","wikidata":"https://www.wikidata.org/wiki/Q192727","display_name":"Physical layer","level":3,"score":0.10221549868583679},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"mag:2183177152","doi":null,"is_oa":false,"landing_page_url":"http://ijcst.com/vol24/3/asutosh.pdf","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W1509600527","https://openalex.org/W1576994491"],"related_works":["https://openalex.org/W7098480983","https://openalex.org/W122780898","https://openalex.org/W2371763732","https://openalex.org/W2013912619","https://openalex.org/W2095157217","https://openalex.org/W2351257668","https://openalex.org/W2138197427","https://openalex.org/W7096049796","https://openalex.org/W2327536561","https://openalex.org/W2957422867"],"abstract_inverted_index":{"USB":[0,22,39,54],"has":[1],"become":[2],"a":[3,34,93],"popular":[4],"interface":[5,23,58],"for":[6,71],"exchanging":[7],"data":[8,82],"between":[9],"PC\u2019s":[10],"and":[11,31,61,77,97,102],"peripherals.":[12],"An":[13],"increasing":[14],"number":[15],"of":[16,33,37,69],"portable":[17],"peripherals":[18],"are":[19],"using":[20],"the":[21,27,38,53,62,66,84,98],"to":[24],"communicate":[25],"with":[26,52,92],"PC.":[28],"The":[29,48],"design":[30],"implementation":[32],"synthesizable":[35],"model":[36,85,99],"1.1":[40,55],"protocol":[41],"engine":[42],"is":[43,50,86],"presented":[44],"in":[45,89],"this":[46],"report":[47],"PHY":[49],"compatible":[51],"transceiver":[56],"macrocell":[57],"(UTMI)":[59],"specification":[60],"simulation":[63],"test":[64],"confirmed":[65],"successful":[67],"operation":[68],"circuits":[70],"both":[72],"full":[73],"speed":[74,79],"(12":[75],"Mbps)":[76,81],"low":[78],"(1.5":[80],"transmission.":[83],"written":[87],"completely":[88],"behavioral":[90],"vhdl":[91],"top":[94],"down":[95],"approach":[96],"was":[100],"verified":[101],"validated.":[103]},"counts_by_year":[],"updated_date":"2025-11-06T04:12:42.849631","created_date":"2016-06-24T00:00:00"}
