{"id":"https://openalex.org/W2172270979","doi":"https://doi.org/10.1049/el:19951367","title":"Analogue VLSI morphological image processing circuit","display_name":"Analogue VLSI morphological image processing circuit","publication_year":1995,"publication_date":"1995-11-09","ids":{"openalex":"https://openalex.org/W2172270979","doi":"https://doi.org/10.1049/el:19951367","mag":"2172270979"},"language":"en","primary_location":{"id":"doi:10.1049/el:19951367","doi":"https://doi.org/10.1049/el:19951367","is_oa":false,"landing_page_url":"https://doi.org/10.1049/el:19951367","pdf_url":null,"source":{"id":"https://openalex.org/S149016011","display_name":"Electronics Letters","issn_l":"0013-5194","issn":["0013-5194","1350-911X"],"is_oa":false,"is_in_doaj":true,"is_core":true,"listed_in":["cwts-core","doaj","dongbi-d","jufo-1","norway-1","oarl","poland-70","russia-white-list-2","vabb-shw"],"host_organization":"https://openalex.org/P4310311714","host_organization_name":"Institution of Engineering and Technology","host_organization_lineage":["https://openalex.org/P4310311714"],"host_organization_lineage_names":["Institution of Engineering and Technology"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Electronics Letters","raw_type":"journal-article"},"volume":null,"type":"article","is_traditional":true,"indexed_in":["crossref","doaj"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111493410","display_name":"T.G. Morris","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"T.G. Morris","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0250, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0250, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013907683","display_name":"Stephen P. DeWeerth","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S.P. DeWeerth","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0250, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0250, USA","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I130701444"],"apc_list":{"value":2590,"currency":"USD","value_usd":2590},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.0,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"31","issue":"23","first_page":"1998","last_page":"1999"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.5375999808311462,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.5375999808311462,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12923","display_name":"Digital Image Processing Techniques","score":0.13650000095367432,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.10159999877214432,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/analog-vlsi","display_name":"analog VLSI","score":0.9309999942779541},{"id":"https://openalex.org/keywords/mathematical-morphology","display_name":"mathematical morphology","score":0.996999979019165},{"id":"https://openalex.org/keywords/dilation","display_name":"dilation","score":0.8889999985694885},{"id":"https://openalex.org/keywords/structuring-elements","display_name":"structuring elements","score":0.8240000009536743},{"id":"https://openalex.org/keywords/massively-parallel-architectures","display_name":"massively parallel architectures","score":0.6639999747276306},{"id":"https://openalex.org/keywords/focal-plane","display_name":"focal plane","score":0.4790000021457672},{"id":"https://openalex.org/keywords/low-power-computation","display_name":"low-power computation","score":0.625},{"id":"https://openalex.org/keywords/high-speed-image-processing","display_name":"high-speed image processing","score":0.6819999814033508}],"concepts":[{"id":"https://openalex.org/C74032544","wikidata":"https://www.wikidata.org/wiki/Q7625238","display_name":"Structuring element","level":5,"score":0.9106409549713135},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.8947222232818604},{"id":"https://openalex.org/C190475519","wikidata":"https://www.wikidata.org/wiki/Q544384","display_name":"Massively parallel","level":2,"score":0.6643906235694885},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6170778274536133},{"id":"https://openalex.org/C2780757906","wikidata":"https://www.wikidata.org/wiki/Q5276676","display_name":"Dilation (metric space)","level":2,"score":0.6070943474769592},{"id":"https://openalex.org/C9417928","wikidata":"https://www.wikidata.org/wiki/Q1070689","display_name":"Image processing","level":3,"score":0.606505274772644},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.4363185167312622},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4332256615161896},{"id":"https://openalex.org/C185568154","wikidata":"https://www.wikidata.org/wiki/Q530242","display_name":"Mathematical morphology","level":4,"score":0.43144428730010986},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.43099427223205566},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3639022707939148},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.32864832878112793},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.2731267809867859},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.2554394006729126},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19194507598876953},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.14183306694030762},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.10207170248031616},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0894310474395752},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1049/el:19951367","doi":"https://doi.org/10.1049/el:19951367","is_oa":false,"landing_page_url":"https://doi.org/10.1049/el:19951367","pdf_url":null,"source":{"id":"https://openalex.org/S149016011","display_name":"Electronics Letters","issn_l":"0013-5194","issn":["0013-5194","1350-911X"],"is_oa":false,"is_in_doaj":true,"is_core":true,"listed_in":["cwts-core","doaj","dongbi-d","jufo-1","norway-1","oarl","poland-70","russia-white-list-2","vabb-shw"],"host_organization":"https://openalex.org/P4310311714","host_organization_name":"Institution of Engineering and Technology","host_organization_lineage":["https://openalex.org/P4310311714"],"host_organization_lineage_names":["Institution of Engineering and Technology"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Electronics Letters","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.47.1417","doi":null,"is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.47.1417","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ee.gatech.edu/research/labs/ccss/publications/tonia/tonia5.ps","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1516966573","https://openalex.org/W1970518142","https://openalex.org/W2051385641","https://openalex.org/W2064619185","https://openalex.org/W2139016795","https://openalex.org/W2139288308","https://openalex.org/W2145597154"],"related_works":["https://openalex.org/W2139288308","https://openalex.org/W2172283028","https://openalex.org/W1896512998","https://openalex.org/W2097333386","https://openalex.org/W2058298109","https://openalex.org/W2054682211","https://openalex.org/W1516966573","https://openalex.org/W2110833446","https://openalex.org/W822057594","https://openalex.org/W2051056409"],"abstract_inverted_index":{"An":[0],"analogue":[1,43,53],"VLSI":[2,44],"circuit":[3,17,54],"that":[4],"performs":[5],"morphological":[6,32,59],"image":[7,33],"processing":[8,34],"operations":[9,35],"on":[10],"the":[11,29,38,57,70,75],"focal":[12],"plane":[13],"is":[14],"presented.":[15],"The":[16,52],"has":[18],"been":[19],"fabricated":[20],"using":[21,37],"a":[22],"standard":[23],"digital":[24],"CMOS":[25],"process.":[26],"We":[27],"exploit":[28],"parallelism":[30],"of":[31,42,61,69],"by":[36],"massively":[39],"parallel":[40],"architecture":[41],"arrays,":[45],"achieving":[46],"both":[47],"high-speed":[48],"and":[49],"low-power":[50],"computation.":[51],"presented":[55],"computes":[56],"grey-scale":[58],"operation":[60],"dilation.":[62],"This":[63],"system":[64],"also":[65],"allows":[66],"for":[67],"programmability":[68],"structuring":[71],"element":[72],"used":[73],"in":[74],"dilation":[76],"operation.":[77]},"counts_by_year":[],"updated_date":"2026-10-16T09:59:22.235173","created_date":"2016-06-24T00:00:00"}
