{"id":"https://openalex.org/W2170786409","doi":"https://doi.org/10.1109/iccd.1993.393329","title":"The Splash 2 processor and applications","display_name":"The Splash 2 processor and applications","publication_year":2002,"publication_date":"2002-12-30","ids":{"openalex":"https://openalex.org/W2170786409","doi":"https://doi.org/10.1109/iccd.1993.393329","mag":"2170786409"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.1993.393329","doi":"https://doi.org/10.1109/iccd.1993.393329","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.1993.393329","pdf_url":null,"source":{"id":"https://openalex.org/S4210174938","display_name":"IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD)","issn_l":"1063-6404","issn":["1063-6404","2576-6996"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":["jufo-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5021349176","display_name":"Jeffrey M. Arnold","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"J.M. Arnold","raw_affiliation_strings":["IDA Supercomputing Research Center, Bowie, MD, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IDA Supercomputing Research Center, Bowie, MD, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031591405","display_name":"Duncan A. Buell","orcid":"https://orcid.org/0000-0002-4668-5848","observed_orcids":["https://orcid.org/0000-0002-4668-5848"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"D.A. Buell","raw_affiliation_strings":["IDA Supercomputing Research Center, Bowie, MD, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IDA Supercomputing Research Center, Bowie, MD, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108190472","display_name":"Dzung T. Hoang","orcid":"https://orcid.org/0000-0003-4806-8082","observed_orcids":["https://orcid.org/0000-0003-4806-8082"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"D.T. Hoang","raw_affiliation_strings":["IDA Supercomputing Research Center, Bowie, MD, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IDA Supercomputing Research Center, Bowie, MD, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088009579","display_name":"Daniel V. Pryor","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"D.V. Pryor","raw_affiliation_strings":["IDA Supercomputing Research Center, Bowie, MD, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IDA Supercomputing Research Center, Bowie, MD, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111466983","display_name":"Nabeel Shirazi","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"N. Shirazi","raw_affiliation_strings":["IDA Supercomputing Research Center, Bowie, MD, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IDA Supercomputing Research Center, Bowie, MD, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043644872","display_name":"M.R. Thistle","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"M.R. Thistle","raw_affiliation_strings":["IDA Supercomputing Research Center, Bowie, MD, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IDA Supercomputing Research Center, Bowie, MD, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.0099,"has_fulltext":false,"cited_by_count":37,"citation_normalized_percentile":{"value":0.92093541,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":88,"max":93},"biblio":{"volume":null,"issue":null,"first_page":"482","last_page":"485"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9833999872207642,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9833999872207642,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.013000000268220901,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":0.00139999995008111,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/splash-2","display_name":"SPLASH-2","score":0.9660000205039978},{"id":"https://openalex.org/keywords/fpga","display_name":"FPGA","score":0.8759999871253967},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.7929999828338623},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"logic synthesis","score":0.7670000195503235},{"id":"https://openalex.org/keywords/automatic-placement-and-routing","display_name":"automatic placement and routing","score":0.9179999828338623},{"id":"https://openalex.org/keywords/hardware-acceleration","display_name":"hardware acceleration","score":0.4620000123977661},{"id":"https://openalex.org/keywords/temporal-parallelism","display_name":"temporal parallelism","score":0.6660000085830688},{"id":"https://openalex.org/keywords/data-parallelism","display_name":"data parallelism","score":0.9789999723434448},{"id":"https://openalex.org/keywords/text-search","display_name":"text search","score":0.7229999899864197},{"id":"https://openalex.org/keywords/sequence-analysis","display_name":"sequence analysis","score":0.9959999918937683},{"id":"https://openalex.org/keywords/image-processing","display_name":"image processing","score":0.824999988079071},{"id":"https://openalex.org/keywords/c-library","display_name":"C++ library","score":0.5550000071525574}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8019759654998779},{"id":"https://openalex.org/C2780644530","wikidata":"https://www.wikidata.org/wiki/Q656906","display_name":"Splash","level":2,"score":0.781971275806427},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6839379668235779},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.6472187638282776},{"id":"https://openalex.org/C2778485113","wikidata":"https://www.wikidata.org/wiki/Q193231","display_name":"Debugger","level":3,"score":0.5930461883544922},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.49724701046943665},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.4472160339355469},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.4345104992389679},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.4257926940917969},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.41134825348854065},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3925301134586334},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33108004927635193},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.2606768310070038},{"id":"https://openalex.org/C153294291","wikidata":"https://www.wikidata.org/wiki/Q25261","display_name":"Meteorology","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.1993.393329","doi":"https://doi.org/10.1109/iccd.1993.393329","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.1993.393329","pdf_url":null,"source":{"id":"https://openalex.org/S4210174938","display_name":"IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD)","issn_l":"1063-6404","issn":["1063-6404","2576-6996"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":["jufo-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1597088765","https://openalex.org/W2142574874","https://openalex.org/W2166907065","https://openalex.org/W2171455717","https://openalex.org/W4239023471"],"related_works":["https://openalex.org/W3004350534","https://openalex.org/W7003268222","https://openalex.org/W1979547397","https://openalex.org/W2171455717","https://openalex.org/W2126618974","https://openalex.org/W2124213963","https://openalex.org/W6926443194","https://openalex.org/W1993923861","https://openalex.org/W1819329817","https://openalex.org/W7097243007"],"abstract_inverted_index":{"Splash":[0,19,119],"2":[1,20,120],"is":[2,21,63,72,86],"an":[3,61],"attached":[4],"parallel":[5],"processor":[6],"in":[7,48,69],"which":[8,29,50],"the":[9,25,90,115],"computing":[10],"elements":[11],"are":[12,41,51],"user-programmable":[13],"FPGA":[14,91,103],"devices.":[15],"The":[16,83,118],"architecture":[17,92],"of":[18,27,35,46,131],"designed":[22],"to":[23,65,74,99,125],"accelerate":[24],"solution":[26],"problems":[28],"exhibit":[30],"at":[31],"least":[32],"modest":[33],"amounts":[34],"temporal":[36],"or":[37],"data":[38],"parallelism.":[39],"Applications":[40],"developed":[42],"by":[43,80,93],"writing":[44],"descriptions":[45],"algorithms":[47],"VHDL,":[49],"then":[52,87],"iteratively":[53],"refined":[54],"and":[55,78,96,110,138],"debugged":[56],"within":[57],"a":[58,75,101,111,129],"simulator.":[59],"Once":[60],"application":[62],"determined":[64],"be":[66,126],"functionally":[67],"correct":[68],"simulation,":[70],"it":[71],"compiled":[73],"gate":[76,84],"list":[77,85],"optimized":[79],"logic":[81],"synthesis.":[82],"mapped":[88],"onto":[89],"automatic":[94],"placement":[95],"routing":[97],"tools":[98],"form":[100],"loadable":[102],"object":[104],"module.":[105],"A":[106],"C":[107],"language":[108],"library":[109],"symbolic":[112],"debugger":[113],"comprise":[114],"execution":[116],"environment.":[117],"system":[121],"has":[122],"been":[123],"shown":[124],"effective":[127],"on":[128],"variety":[130],"applications,":[132],"including":[133],"text":[134],"searching,":[135],"sequence":[136],"analysis,":[137],"image":[139],"processing.>":[140]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-11-04T10:54:05.112534","created_date":"2016-06-24T00:00:00"}