{"id":"https://openalex.org/W2167940947","doi":"https://doi.org/10.1109/fpl.2008.4629900","title":"Modeling recursion data structures for FPGA-based implementation","display_name":"Modeling recursion data structures for FPGA-based implementation","publication_year":2008,"publication_date":"2008-01-01","ids":{"openalex":"https://openalex.org/W2167940947","doi":"https://doi.org/10.1109/fpl.2008.4629900","mag":"2167940947"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2008.4629900","doi":"https://doi.org/10.1109/fpl.2008.4629900","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2008.4629900","pdf_url":null,"source":{"id":"https://openalex.org/S7407085929","display_name":"International Conference on Field Programmable Logic and Applications (FPL)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5097038460","display_name":"Spyridon Ninos","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I55741626","display_name":"Technical University of Crete","ror":"https://ror.org/03f8bz564","country_code":"GR","type":"education","lineage":["https://openalex.org/I55741626"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Spyridon Ninos","raw_affiliation_strings":["Microprocessor and Hardware Laboratory, Department of Electronic and Computer Engineering, Technical University of Crete, Chania, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor and Hardware Laboratory, Department of Electronic and Computer Engineering, Technical University of Crete, Chania, Greece","institution_ids":["https://openalex.org/I55741626"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5056983242","display_name":"Apostolos Dollas","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I55741626","display_name":"Technical University of Crete","ror":"https://ror.org/03f8bz564","country_code":"GR","type":"education","lineage":["https://openalex.org/I55741626"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Apostolos Dollas","raw_affiliation_strings":["Microprocessor and Hardware Laboratory, Department of Electronic and Computer Engineering, Technical University of Crete, Chania, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor and Hardware Laboratory, Department of Electronic and Computer Engineering, Technical University of Crete, Chania, Greece","institution_ids":["https://openalex.org/I55741626"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I55741626"],"apc_list":null,"apc_paid":null,"fwci":2.3127,"has_fulltext":false,"cited_by_count":20,"citation_normalized_percentile":{"value":0.88948307,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":87,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"11","last_page":"16"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9883000254631042,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9883000254631042,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":0.0066999997943639755,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.0034000000450760126,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/recursion","display_name":"recursion","score":0.9279999732971191},{"id":"https://openalex.org/keywords/fpga-implementation","display_name":"FPGA implementation","score":0.7429999709129333},{"id":"https://openalex.org/keywords/reconfigurable-hardware","display_name":"reconfigurable hardware","score":0.8650000095367432},{"id":"https://openalex.org/keywords/hardware-architecture","display_name":"hardware architecture","score":0.45100000500679016},{"id":"https://openalex.org/keywords/recursive-algorithm","display_name":"recursive algorithm","score":0.5979999899864197},{"id":"https://openalex.org/keywords/hardware-acceleration","display_name":"hardware acceleration","score":0.5569999814033508},{"id":"https://openalex.org/keywords/area-utilization","display_name":"area utilization","score":0.7289999723434448},{"id":"https://openalex.org/keywords/speedup","display_name":"speedup","score":0.6880000233650208}],"concepts":[{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.9114797115325928},{"id":"https://openalex.org/C168773036","wikidata":"https://www.wikidata.org/wiki/Q264164","display_name":"Recursion (computer science)","level":2,"score":0.8782186508178711},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8247241377830505},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6909145712852478},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.6860494613647461},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6639817953109741},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5496464967727661},{"id":"https://openalex.org/C162319229","wikidata":"https://www.wikidata.org/wiki/Q175263","display_name":"Data structure","level":2,"score":0.43097859621047974},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4053623080253601},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3911077082157135},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.32591432332992554},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.26017463207244873},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.20261970162391663}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/fpl.2008.4629900","doi":"https://doi.org/10.1109/fpl.2008.4629900","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2008.4629900","pdf_url":null,"source":{"id":"https://openalex.org/S7407085929","display_name":"International Conference on Field Programmable Logic and Applications (FPL)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1559704775","https://openalex.org/W2116324949","https://openalex.org/W2126380235","https://openalex.org/W2128453758","https://openalex.org/W2149406387","https://openalex.org/W2158068912","https://openalex.org/W2167097446"],"related_works":["https://openalex.org/W2116324949","https://openalex.org/W2128453758","https://openalex.org/W2098175220","https://openalex.org/W2016580664","https://openalex.org/W2126380235","https://openalex.org/W1969431472","https://openalex.org/W2149406387","https://openalex.org/W2006790606","https://openalex.org/W3132362584","https://openalex.org/W1994983121"],"abstract_inverted_index":{"Recursion":[0],"is":[1,13,22,36,110],"a":[2,14,29,71],"powerful":[3],"technique":[4],"used":[5],"to":[6,27,32,39],"solve":[7],"problems":[8],"with":[9],"repeating":[10],"patterns,":[11],"and":[12,44,61,104,116],"fundamental":[15],"structure":[16],"in":[17,70],"software.":[18],"To":[19],"date":[20],"there":[21],"no":[23],"known":[24],"general":[25,72,118],"way":[26,73],"apply":[28],"recursive":[30],"solution":[31],"reconfigurable":[33],"hardware;":[34],"it":[35,109],"considered":[37],"difficult":[38],"implement,":[40],"of":[41],"low":[42],"performance":[43],"resource-intensive.":[45],"In":[46],"this":[47],"paper":[48],"we":[49,62],"extend":[50],"previous":[51],"results":[52],"on":[53,74],"hardware":[54,122],"structures":[55],"for":[56],"recursion":[57,65],"by":[58],"V.":[59],"Sklyarov,":[60],"demonstrate":[63],"that":[64,78],"can":[66],"be":[67],"efficiently":[68],"implemented":[69],"FPGAs.":[75],"We":[76],"show":[77],"our":[79],"general,":[80],"non-optimized":[81],"architecture":[82],"presents":[83],"approximately":[84],"3":[85],"times":[86],"speedup":[87],"against":[88],"optimized":[89],"software":[90],"algorithm":[91],"implementations.":[92,123],"It":[93],"also":[94],"shows":[95],"75%":[96],"speedup,":[97],"at":[98,105],"least":[99],"40%":[100],"lower":[101],"area":[102],"utilization,":[103],"the":[106],"same":[107],"time":[108,114],"simpler,":[111],"less":[112],"designer":[113],"consuming":[115],"more":[117],"vs.":[119],"previously":[120],"published":[121]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-11-10T11:39:43.021295","created_date":"2016-06-24T00:00:00"}