{"id":"https://openalex.org/W2157239686","doi":null,"title":"The C compiler generating a source file in VHDL for a dynamic dataflow machine being executed direct into a hardware","display_name":"The C compiler generating a source file in VHDL for a dynamic dataflow machine being executed direct into a hardware","publication_year":2009,"publication_date":"2009-12-01","ids":{"openalex":"https://openalex.org/W2157239686","mag":"2157239686"},"language":"en","primary_location":{"id":"pmh:oai:CiteSeerX.psu:10.1.1.559.2904","doi":null,"is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.559.2904","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.wseas.us/e-library/transactions/computers/2009/32-812.pdf","raw_type":"text"},"parent_works":[],"lineage":["https://openalex.org/W2157239686"],"child_works_count":0,"type":"article","is_traditional":true,"indexed_in":[],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5087439754","display_name":"Jorge Luiz e Silva","orcid":"https://orcid.org/0000-0003-1119-7323","observed_orcids":["https://orcid.org/0000-0003-1119-7323"]},"institutions":[{"id":"https://openalex.org/I17974374","display_name":"Universidade de S\u00e3o Paulo","ror":"https://ror.org/036rp1748","country_code":"BR","type":"education","lineage":["https://openalex.org/I17974374"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Jorge Luiz e Silva","raw_affiliation_strings":["University of Sao Paulo, Department of Computer Systems, Brazil#TAB#"],"raw_orcid":"https://orcid.org/0000-0003-1119-7323","affiliations":[{"raw_affiliation_string":"University of Sao Paulo, Department of Computer Systems, Brazil#TAB#","institution_ids":["https://openalex.org/I17974374"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000302987","display_name":"Kelton Augusto Pontara da Costa","orcid":"https://orcid.org/0000-0001-5458-3908","observed_orcids":["https://orcid.org/0000-0001-5458-3908"]},"institutions":[{"id":"https://openalex.org/I17974374","display_name":"Universidade de S\u00e3o Paulo","ror":"https://ror.org/036rp1748","country_code":"BR","type":"education","lineage":["https://openalex.org/I17974374"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Kelton Augusto Pontara da Costa","raw_affiliation_strings":["University of S\u00e3o Paulo, School of Engineering of S\u00e3o Carlos, Brazil"],"raw_orcid":"https://orcid.org/0000-0001-5458-3908","affiliations":[{"raw_affiliation_string":"University of S\u00e3o Paulo, School of Engineering of S\u00e3o Carlos, Brazil","institution_ids":["https://openalex.org/I17974374"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5050993432","display_name":"Valentin Obac Roda","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I17974374","display_name":"Universidade de S\u00e3o Paulo","ror":"https://ror.org/036rp1748","country_code":"BR","type":"education","lineage":["https://openalex.org/I17974374"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Valent\u00edn Obac Roda","raw_affiliation_strings":["University of S\u00e3o Paulo, School of Engineering of S\u00e3o Carlos, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of S\u00e3o Paulo, School of Engineering of S\u00e3o Carlos, Brazil","institution_ids":["https://openalex.org/I17974374"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I17974374"],"apc_list":null,"apc_paid":null,"fwci":1.1959,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.81169167,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":88,"max":93},"biblio":{"volume":"8","issue":"12","first_page":"1908","last_page":"1916"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":9.999999747378752e-05,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":9.999999747378752e-05,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/c-compiler","display_name":"C compiler","score":0.8769999742507935},{"id":"https://openalex.org/keywords/vhdl-implementation","display_name":"VHDL implementation","score":0.6890000104904175},{"id":"https://openalex.org/keywords/dataflow-architecture","display_name":"dataflow architecture","score":0.5680000185966492}],"concepts":[{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.9667660593986511},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8985865116119385},{"id":"https://openalex.org/C176727019","wikidata":"https://www.wikidata.org/wiki/Q1172415","display_name":"Dataflow architecture","level":3,"score":0.7709156274795532},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.7407615780830383},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.6646004319190979},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.6284474730491638},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.5695681571960449},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5676393508911133},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.5165016055107117},{"id":"https://openalex.org/C88468194","wikidata":"https://www.wikidata.org/wiki/Q1172416","display_name":"Data-flow analysis","level":3,"score":0.4749760031700134},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4704510271549225},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.3483573794364929},{"id":"https://openalex.org/C489000","wikidata":"https://www.wikidata.org/wiki/Q747385","display_name":"Data flow diagram","level":2,"score":0.3212006688117981},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2695150077342987},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.233384907245636},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"pmh:oai:CiteSeerX.psu:10.1.1.559.2904","doi":null,"is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.559.2904","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.wseas.us/e-library/transactions/computers/2009/32-812.pdf","raw_type":"text"},{"id":"mag:2157239686","doi":null,"is_oa":false,"landing_page_url":"http://www.wseas.us/e-library/transactions/computers/2009/32-812.pdf","pdf_url":null,"source":{"id":"https://openalex.org/S2765062798","display_name":"WSEAS Transactions on Computers archive","issn_l":"1109-2750","issn":["1109-2750","2224-2872"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["anvur-scientific","cwts-core"],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":"WSEAS Transactions on Computers archive","raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1543657314","https://openalex.org/W1607573553","https://openalex.org/W1976417857","https://openalex.org/W2030375827","https://openalex.org/W2041502581","https://openalex.org/W2118412448","https://openalex.org/W2137380783","https://openalex.org/W2532264403","https://openalex.org/W2534121101","https://openalex.org/W2984906857"],"related_works":["https://openalex.org/W1537707312","https://openalex.org/W1984166283","https://openalex.org/W1592756059","https://openalex.org/W2616551022","https://openalex.org/W2916677998","https://openalex.org/W2116349307","https://openalex.org/W197043460","https://openalex.org/W7099817726","https://openalex.org/W1550035419"],"abstract_inverted_index":{"Abstract:":[0],"In":[1,90],"order":[2,116],"to":[3,20,24,43,51,70,96,117],"convert":[4,44,71,97],"High":[5],"Level":[6],"Language":[7],"(HLL)":[8],"into":[9,46,75,99],"hardware,":[10,57],"a":[11,17,41,47,76,93,100,119],"Control":[12],"Dataflow":[13,26],"Graph":[14],"(CDFG)":[15],"is":[16,38,109],"fundamental":[18],"element":[19],"be":[21,29,52],"used.":[22],"Related":[23],"this,":[25],"Architecture,":[27],"can":[28],"obtained":[30],"directly":[31],"from":[32],"the":[33,59,68,72,79,84,87,104,122],"CDFG.":[34],"The":[35,62],"ChipCflow":[36,63],"project":[37],"described":[39],"as":[40],"system":[42],"HLL":[45],"dynamic":[48,55,60],"dataflow":[49,77,101],"graph":[50,102,105],"executed":[53],"in":[54,107,115],"reconfigurable":[56],"exploring":[58],"reconfiguration.":[61],"consists":[64],"of":[65],"various":[66],"parts:":[67],"compiler":[69,95],"C":[73,94,98],"program":[74],"graph;":[78],"operators":[80],"and":[81,86,103],"its":[82],"instances;":[83],"tagged-token;":[85],"matching":[88],"data.":[89],"this":[91],"paper,":[92],"implementation":[106],"VHDL":[108],"described.":[110],"Some":[111],"results":[112],"are":[113],"presented":[114],"show":[118],"proof-of-concept":[120],"for":[121],"project.":[123]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-11-14T11:04:58.165337","created_date":"2016-06-24T00:00:00"}