{"id":"https://openalex.org/W2154458184","doi":"https://doi.org/10.1109/hpcsim.2011.5999870","title":"Evaluation and improvements of programming models for the Intel SCC many-core processor","display_name":"Evaluation and improvements of programming models for the Intel SCC many-core processor","publication_year":2011,"publication_date":"2011-07-01","ids":{"openalex":"https://openalex.org/W2154458184","doi":"https://doi.org/10.1109/hpcsim.2011.5999870","mag":"2154458184"},"language":"en","primary_location":{"id":"doi:10.1109/hpcsim.2011.5999870","doi":"https://doi.org/10.1109/hpcsim.2011.5999870","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpcsim.2011.5999870","pdf_url":null,"source":{"id":"https://openalex.org/S7407088274","display_name":"International Conference on High Performance Computing & Simulation (HPCS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 International Conference on High Performance Computing &amp; Simulation","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006061846","display_name":"Carsten Clau\u00df","orcid":"https://orcid.org/0000-0002-9292-4192","observed_orcids":["https://orcid.org/0000-0002-9292-4192"]},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Carsten Clauss","raw_affiliation_strings":["Operation Systems, RWTH Aachen University, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Operation Systems, RWTH Aachen University, Germany","institution_ids":["https://openalex.org/I887968799"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050707009","display_name":"Stefan Lankes","orcid":"https://orcid.org/0000-0003-4718-2238","observed_orcids":["https://orcid.org/0000-0003-4718-2238"]},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Stefan Lankes","raw_affiliation_strings":["Operation Systems, RWTH Aachen University, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Operation Systems, RWTH Aachen University, Germany","institution_ids":["https://openalex.org/I887968799"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001901526","display_name":"Pablo Reble","orcid":"https://orcid.org/0009-0002-2544-5535","observed_orcids":["https://orcid.org/0009-0002-2544-5535"]},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Pablo Reble","raw_affiliation_strings":["Operation Systems, RWTH Aachen University, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Operation Systems, RWTH Aachen University, Germany","institution_ids":["https://openalex.org/I887968799"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5060198678","display_name":"Thomas Bemmerl","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Thomas Bemmerl","raw_affiliation_strings":["Operation Systems, RWTH Aachen University, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Operation Systems, RWTH Aachen University, Germany","institution_ids":["https://openalex.org/I887968799"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I887968799"],"apc_list":null,"apc_paid":null,"fwci":8.2119,"has_fulltext":false,"cited_by_count":58,"citation_normalized_percentile":{"value":0.98532218,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":88,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"525","last_page":"532"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.001500000013038516,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.00039999998989515007,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/many-core-processors","display_name":"many-core processors","score":0.8610000014305115},{"id":"https://openalex.org/keywords/programming-models","display_name":"programming models","score":0.6819999814033508},{"id":"https://openalex.org/keywords/message-passing","display_name":"message passing","score":0.8640000224113464},{"id":"https://openalex.org/keywords/shared-memory-programming","display_name":"shared memory programming","score":0.9599999785423279},{"id":"https://openalex.org/keywords/memory-partitioning","display_name":"memory partitioning","score":0.6769999861717224}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8606053590774536},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.7628070116043091},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.6639236807823181},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.6484572291374207},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5676264762878418},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5357851982116699},{"id":"https://openalex.org/C34165917","wikidata":"https://www.wikidata.org/wiki/Q188267","display_name":"Programming paradigm","level":2,"score":0.5248417854309082},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5074581503868103},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.46462589502334595},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.43425253033638},{"id":"https://openalex.org/C133371097","wikidata":"https://www.wikidata.org/wiki/Q868014","display_name":"Non-uniform memory access","level":5,"score":0.42564883828163147},{"id":"https://openalex.org/C51185590","wikidata":"https://www.wikidata.org/wiki/Q1017228","display_name":"Bus sniffing","level":5,"score":0.42492181062698364},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.4222668409347534},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4123538136482239},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.3906896710395813},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.3658517599105835},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.3469007611274719},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.09989923238754272}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/hpcsim.2011.5999870","doi":"https://doi.org/10.1109/hpcsim.2011.5999870","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpcsim.2011.5999870","pdf_url":null,"source":{"id":"https://openalex.org/S7407088274","display_name":"International Conference on High Performance Computing & Simulation (HPCS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 International Conference on High Performance Computing &amp; Simulation","raw_type":"proceedings-article"},{"id":"pmh:oai:publications.rwth-aachen.de:128568","doi":null,"is_oa":false,"landing_page_url":"https://publications.rwth-aachen.de/search?p=id:%22RWTH-CONV-198655%22","pdf_url":null,"source":{"id":"https://openalex.org/S4306401362","display_name":"RWTH Publications (RWTH Aachen)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I887968799","host_organization_name":"RWTH Aachen University","host_organization_lineage":["https://openalex.org/I887968799"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Proceedings of the 2011 International Conference on High Performance Computing and Simulation (HPCS 2011) : Istanbul, Turkey, 4 - 8 July 2011 ; [including workshop papers] / [in technical cooperation with the ACM; IEEE ... Ed.: Waleed W. Smari]<br/>2011 International Conference on High Performance Computing and Simulation, HPCS 2011, Istanbul, Turkey, 2011-07-04 - 2011-07-08","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320307102","display_name":"Intel Corporation","ror":"https://ror.org/01ek73717"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1527044604","https://openalex.org/W1963637299","https://openalex.org/W2035015266","https://openalex.org/W2081612620","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W1583458699","https://openalex.org/W2070125609","https://openalex.org/W1963637299","https://openalex.org/W626390526","https://openalex.org/W7095680192","https://openalex.org/W2110954112","https://openalex.org/W4253127868","https://openalex.org/W2406332351","https://openalex.org/W1967004358","https://openalex.org/W2019629740"],"abstract_inverted_index":{"Since":[0],"the":[1,4,13,46,61,77,133,148,160,187,194,213],"beginning":[2],"of":[3,45,48,196],"multicore":[5,18],"era,":[6],"parallel":[7],"processing":[8],"has":[9],"become":[10],"prevalent":[11],"across":[12],"board.":[14],"On":[15],"a":[16,20,42,66,84,90,99,109,115,138],"traditional":[17],"system,":[19],"single":[21],"operating":[22,126],"system":[23,51,127],"manages":[24],"all":[25],"cores":[26,49],"and":[27,30,81,155,183,200],"schedules":[28],"threads":[29],"processes":[31],"among":[32],"them,":[33],"inherently":[34],"supported":[35],"by":[36,131,166],"hardware-implemented":[37],"cache":[38,62,79,161],"coherence":[39,63],"protocols.":[40,64],"However,":[41,141],"further":[43],"growth":[44],"number":[47],"per":[50,129],"implies":[52],"an":[53,153],"increasing":[54],"chip":[55],"complexity,":[56],"especially":[57,209],"with":[58,103,210],"respect":[59,211],"to":[60,75,82,123,146,212],"Therefore,":[65],"very":[67,110],"attractive":[68],"alternative":[69],"for":[70,113,181],"future":[71],"many-core":[72,100,215],"systems":[73],"is":[74,108,143,163],"waive":[76],"hardware-based":[78],"coherency":[80,162],"introduce":[83],"software-oriented":[85],"message-passing":[86,182],"based":[87],"architecture":[88],"instead:":[89],"so-called":[91],"Cluster-on-Chip":[92,116],"architecture.":[93,117,216],"Intel's":[94],"Single-chip":[95],"Cloud":[96],"Computer":[97],"(SCC),":[98],"research":[101],"processor":[102],"48":[104],"non-coherent":[105],"memory-coupled":[106],"cores,":[107],"recent":[111],"example":[112],"such":[114],"The":[118],"SCC":[119],"can":[120,206],"be":[121,207],"configured":[122],"run":[124],"one":[125],"instance":[128],"core":[130],"partitioning":[132],"shared":[134,149],"main":[135,150],"memory":[136,151],"in":[137,152],"strict":[139],"manner.":[140],"it":[142],"also":[144],"possible":[145],"access":[147],"unsplit":[154],"concurrent":[156],"manner,":[157],"provided":[158],"that":[159],"then":[164],"ensured":[165],"software.":[167],"In":[168,189],"this":[169],"paper,":[170],"we":[171,192,201],"detail":[172],"our":[173],"first":[174],"experiences":[175],"gained":[176],"while":[177],"developing":[178],"low-level":[179],"software":[180],"shared-memory":[184],"programming":[185,198],"on":[186],"SCC.":[188],"doing":[190],"so,":[191],"evaluate":[193],"potential":[195],"both":[197],"models":[199,205],"show":[202],"how":[203],"these":[204],"improved":[208],"SCC's":[214]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":9},{"year":2013,"cited_by_count":7},{"year":2012,"cited_by_count":18}],"updated_date":"2026-11-03T10:50:19.383937","created_date":"2016-06-24T00:00:00"}