{"id":"https://openalex.org/W2154237706","doi":"https://doi.org/10.1109/jssc.2012.2229070","title":"A 0.016-mm$^{2}$ 144-$\\mu$W Three-Stage Amplifier Capable of Driving 1-to-15 nF Capacitive Load With $> $0.95-MHz GBW","display_name":"A 0.016-mm$^{2}$ 144-$\\mu$W Three-Stage Amplifier Capable of Driving 1-to-15 nF Capacitive Load With $> $0.95-MHz GBW","publication_year":2013,"publication_date":"2013-01-08","ids":{"openalex":"https://openalex.org/W2154237706","doi":"https://doi.org/10.1109/jssc.2012.2229070","mag":"2154237706"},"language":"en","primary_location":{"id":"doi:10.1109/jssc.2012.2229070","doi":"https://doi.org/10.1109/jssc.2012.2229070","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2012.2229070","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","dongbi-a","jufo-3","norway-2","poland-140","russia-white-list-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"volume":null,"type":"article","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100888754","display_name":"Zushu Yan","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Zushu Yan","raw_affiliation_strings":["State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058845450","display_name":"Pui\u2010In Mak","orcid":"https://orcid.org/0000-0002-3579-8740","observed_orcids":["https://orcid.org/0000-0002-3579-8740"]},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Pui-In Mak","raw_affiliation_strings":["State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109927673","display_name":"Man Kay Law","orcid":"https://orcid.org/0000-0002-2799-1129","observed_orcids":["https://orcid.org/0000-0002-2799-1129"]},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Man-Kay Law","raw_affiliation_strings":["State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5106943352","display_name":"Rui Paulo Martins","orcid":"https://orcid.org/0000-0003-2821-648X","observed_orcids":["https://orcid.org/0000-0003-2821-648X"]},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]},{"id":"https://openalex.org/I4387152517","display_name":"Instituto Superior T\u00e9cnico","ror":"https://ror.org/03db2by73","country_code":"PT","type":"education","lineage":["https://openalex.org/I141596103","https://openalex.org/I4387152517"]},{"id":"https://openalex.org/I4405264366","display_name":"Universidade T\u00e9cnica de Lisboa","ror":"https://ror.org/01qc02b16","country_code":"PT","type":"education","lineage":["https://openalex.org/I141596103","https://openalex.org/I4405264366"]}],"countries":["MO","PT"],"is_corresponding":false,"raw_author_name":"Rui P. Martins","raw_affiliation_strings":["Instituto Superior T\u00e9cnico, Technical University of Lisbon, Portugal","State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Instituto Superior T\u00e9cnico, Technical University of Lisbon, Portugal","institution_ids":["https://openalex.org/I4387152517","https://openalex.org/I4405264366"]},{"raw_affiliation_string":"State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":2645,"currency":"USD","value_usd":2645},"apc_paid":null,"fwci":9.6257,"has_fulltext":false,"cited_by_count":148,"citation_normalized_percentile":{"value":0.9847098,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":97,"max":100},"biblio":{"volume":"48","issue":"2","first_page":"527","last_page":"540"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9297000169754028,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9297000169754028,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.06319999694824219,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.004800000227987766,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/three-stage-amplifier","display_name":"three-stage amplifier","score":0.8320000171661377},{"id":"https://openalex.org/keywords/miller-compensation","display_name":"Miller compensation","score":0.8849999904632568},{"id":"https://openalex.org/keywords/gain-bandwidth-product","display_name":"gain-bandwidth product","score":0.8339999914169312},{"id":"https://openalex.org/keywords/slew-rate","display_name":"slew rate","score":0.8330000042915344},{"id":"https://openalex.org/keywords/phase-margin","display_name":"phase margin","score":0.9660000205039978},{"id":"https://openalex.org/keywords/low-power-amplifier","display_name":"low-power amplifier","score":0.6439999938011169},{"id":"https://openalex.org/keywords/pole-zero-placement","display_name":"pole-zero placement","score":0.8199999928474426},{"id":"https://openalex.org/keywords/0-35-mum-cmos","display_name":"0.35 \u03bcm CMOS","score":0.8629999756813049}],"concepts":[{"id":"https://openalex.org/C2776194525","wikidata":"https://www.wikidata.org/wiki/Q282142","display_name":"Glioblastoma","level":2,"score":0.36862605810165405},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.12568265199661255},{"id":"https://openalex.org/C502942594","wikidata":"https://www.wikidata.org/wiki/Q3421914","display_name":"Cancer research","level":1,"score":0.08118495345115662}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/jssc.2012.2229070","doi":"https://doi.org/10.1109/jssc.2012.2229070","is_oa":false,"landing_page_url":"https://doi.org/10.1109/jssc.2012.2229070","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","dongbi-a","jufo-3","norway-2","poland-140","russia-white-list-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.704.40","doi":null,"is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.704.40","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.umac.mo/rectors_office/docs/ruimartins_cv/publications/journalpapers/49.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W1531453206","https://openalex.org/W1531766064","https://openalex.org/W1595764735","https://openalex.org/W1974779192","https://openalex.org/W2016148407","https://openalex.org/W2020763844","https://openalex.org/W2021570329","https://openalex.org/W2056587553","https://openalex.org/W2076027811","https://openalex.org/W2078161049","https://openalex.org/W2081968211","https://openalex.org/W2096710250","https://openalex.org/W2102029541","https://openalex.org/W2103180201","https://openalex.org/W2114557264","https://openalex.org/W2116222529","https://openalex.org/W2125776391","https://openalex.org/W2127639137","https://openalex.org/W2134004455","https://openalex.org/W2161583624","https://openalex.org/W2162080503","https://openalex.org/W2167225414","https://openalex.org/W2167493278","https://openalex.org/W2169238252","https://openalex.org/W3150603910"],"related_works":["https://openalex.org/W7097818179","https://openalex.org/W2584870236","https://openalex.org/W3143961448","https://openalex.org/W2511950361","https://openalex.org/W2337814002","https://openalex.org/W7097057428","https://openalex.org/W2946056280","https://openalex.org/W2161309745","https://openalex.org/W2811358492","https://openalex.org/W3048446860"],"abstract_inverted_index":{"A":[0],"0.016-mm2144-\u03bc":[1],"W":[2],"three-stage":[3],"amplifier":[4],"capable":[5],"of":[6],"driving":[7],"1-to-15-nF":[8],"capacitive":[9],"load":[10],"(CL)":[11],"is":[12,15,97],"described.":[13],"It":[14,96],"optimized":[16],"via":[17],"combining":[18],"current-buffer":[19],"Miller":[20],"compensation":[21],"and":[22,37,52,63,75,86,110],"parasitic-pole":[23],"cancellation":[24],"(via":[25],"an":[26,98],"active":[27],"left-half-plane":[28],"zero":[29],"circuit)":[30],"to":[31,71,81,106],"extend":[32],"theCLdrivability":[33],"with":[34,79],"small":[35],"power":[36],"area.":[38],"Fabricated":[39],"in":[40],"0.35-\u03bc":[41],"m":[42],"CMOS,":[43],"the":[44,103,113],"minimum":[45],"gain-bandwidth":[46],"product":[47],"(GBW),":[48],"slew":[49],"rate":[50],"(SR)":[51],"phase":[53],"margin":[54],"measured":[55],"over":[56],"1-to-15-nFCLare":[57],"0.95":[58],"MHz,":[59],"0.22":[60],"V/":[61],"\u03bcs":[62],"52.3":[64],"\u00b0,":[65],"respectively.":[66],"The":[67,84],"results":[68],"at":[69,112],"15-nFCLcorrespond":[70],"2.02x-improved":[72],"small-signal":[73],"FOMS(=GBW\u00b7CL/Power),":[74],"1.44x-improved":[76],"large-signal":[77],"FOML(=SR\u00b7CL/Power)":[78],"respect":[80],"prior":[82],"art.":[83],"sizing":[85],"optimization":[87],"are":[88],"systematically":[89],"guided":[90],"by":[91],"Local":[92],"Feedback":[93],"Loop":[94],"Analysis.":[95],"insightful":[99],"control-centric":[100],"method":[101],"allowing":[102],"pole-zero":[104],"placements":[105],"be":[107],"more":[108],"analyzable":[109],"comparable":[111],"system":[114],"level.":[115]},"counts_by_year":[{"year":2026,"cited_by_count":4},{"year":2025,"cited_by_count":8},{"year":2024,"cited_by_count":10},{"year":2023,"cited_by_count":9},{"year":2022,"cited_by_count":12},{"year":2021,"cited_by_count":13},{"year":2020,"cited_by_count":10},{"year":2019,"cited_by_count":9},{"year":2018,"cited_by_count":13},{"year":2017,"cited_by_count":11},{"year":2016,"cited_by_count":15},{"year":2015,"cited_by_count":20},{"year":2014,"cited_by_count":9},{"year":2013,"cited_by_count":5}],"updated_date":"2026-11-04T10:54:05.112534","created_date":"2016-06-24T00:00:00"}