{"id":"https://openalex.org/W2144884064","doi":"https://doi.org/10.1109/4.808918","title":"A 0.155-, 0.622-, and 2.488-Gb/s automatic bit-rate selecting clock and data recovery IC for bit-rate transparent SDH systems","display_name":"A 0.155-, 0.622-, and 2.488-Gb/s automatic bit-rate selecting clock and data recovery IC for bit-rate transparent SDH systems","publication_year":1999,"publication_date":"1999-01-01","ids":{"openalex":"https://openalex.org/W2144884064","doi":"https://doi.org/10.1109/4.808918","mag":"2144884064"},"language":"en","primary_location":{"id":"doi:10.1109/4.808918","doi":"https://doi.org/10.1109/4.808918","is_oa":false,"landing_page_url":"https://doi.org/10.1109/4.808918","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","dongbi-a","jufo-3","norway-2","poland-140","russia-white-list-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"volume":null,"type":"article","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5042898125","display_name":"J. Christoph Scheytt","orcid":"https://orcid.org/0000-0002-5950-6618","observed_orcids":["https://orcid.org/0000-0002-5950-6618"]},"institutions":[{"id":"https://openalex.org/I904495901","display_name":"Ruhr University Bochum","ror":"https://ror.org/04tsk2644","country_code":"DE","type":"education","lineage":["https://openalex.org/I904495901"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"J.C. Scheytt","raw_affiliation_strings":["Lehrstuhl f\u00fcr Elektronische Bauelemente, Ruhr Universit\u00e4t Bochum, Bochum, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Lehrstuhl f\u00fcr Elektronische Bauelemente, Ruhr Universit\u00e4t Bochum, Bochum, Germany","institution_ids":["https://openalex.org/I904495901"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046827636","display_name":"G. Hanke","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I904495901","display_name":"Ruhr University Bochum","ror":"https://ror.org/04tsk2644","country_code":"DE","type":"education","lineage":["https://openalex.org/I904495901"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"G. Hanke","raw_affiliation_strings":["Lehrstuhl f\u00fcr Elektronische Bauelemente, Ruhr Universit\u00e4t Bochum, Bochum, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Lehrstuhl f\u00fcr Elektronische Bauelemente, Ruhr Universit\u00e4t Bochum, Bochum, Germany","institution_ids":["https://openalex.org/I904495901"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018713767","display_name":"Ulrich Langmann","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4210093367","display_name":"Deutsche Telekom (Germany)","ror":"https://ror.org/00m8prc86","country_code":"DE","type":"company","lineage":["https://openalex.org/I4210093367"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"U. Langmann","raw_affiliation_strings":["Research Group Optical Multigigabit/s-Systems, Deutsche Telekom AG, Darmstadt, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Research Group Optical Multigigabit/s-Systems, Deutsche Telekom AG, Darmstadt, Germany","institution_ids":["https://openalex.org/I4210093367"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":2645,"currency":"USD","value_usd":2645},"apc_paid":null,"fwci":1.2826,"has_fulltext":false,"cited_by_count":22,"citation_normalized_percentile":{"value":0.80823714,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":87,"max":93},"biblio":{"volume":"34","issue":"12","first_page":"1935","last_page":"1943"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-and-data-recovery","display_name":"clock and data recovery","score":0.9929999709129333},{"id":"https://openalex.org/keywords/synchronous-digital-hierarchy","display_name":"synchronous digital hierarchy","score":0.8230000138282776},{"id":"https://openalex.org/keywords/sonet-sdh","display_name":"SONET/SDH","score":0.7799999713897705},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"phase-locked loop","score":0.9670000076293945},{"id":"https://openalex.org/keywords/jitter","display_name":"jitter","score":0.6299999952316284}],"concepts":[{"id":"https://openalex.org/C198306430","wikidata":"https://www.wikidata.org/wiki/Q51823","display_name":"Synchronous optical networking","level":2,"score":0.7246843576431274},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.7068710327148438},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.6866582036018372},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6140425801277161},{"id":"https://openalex.org/C2779835379","wikidata":"https://www.wikidata.org/wiki/Q2348121","display_name":"Clock recovery","level":4,"score":0.5918139815330505},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5085667371749878},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.46028226613998413},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.44530266523361206},{"id":"https://openalex.org/C529754248","wikidata":"https://www.wikidata.org/wiki/Q1054772","display_name":"Data recovery","level":2,"score":0.41511648893356323},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.3829902708530426},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.25752758979797363},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20311510562896729},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1373460292816162}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/4.808918","doi":"https://doi.org/10.1109/4.808918","is_oa":false,"landing_page_url":"https://doi.org/10.1109/4.808918","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","dongbi-a","jufo-3","norway-2","poland-140","russia-white-list-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1539339959","https://openalex.org/W1567068735","https://openalex.org/W1602813146","https://openalex.org/W2049888220","https://openalex.org/W2101274221","https://openalex.org/W2107204907"],"related_works":["https://openalex.org/W2122913422","https://openalex.org/W3151468864","https://openalex.org/W2129957622","https://openalex.org/W2534094595","https://openalex.org/W2174811807","https://openalex.org/W1972553570","https://openalex.org/W2076935827","https://openalex.org/W2127798176","https://openalex.org/W2120907638","https://openalex.org/W2891044306"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,26,34,39,64],"0.155-,":[4],"0.622-,":[5],"and":[6,12,28,38,51,55,71],"2.488-Gb/s":[7],"automatic":[8],"bit-rate":[9,35,43],"selecting":[10],"clock":[11,27,54],"data":[13,29,56],"recovery":[14,30,57],"circuit":[15,45,60],"for":[16],"transparent":[17],"synchronous":[18],"digital":[19],"hierarchy":[20],"(SDH)":[21],"systems.":[22],"The":[23,59],"IC":[24],"incorporates":[25],"phase-locked":[31],"loop":[32],"(PLL),":[33],"detection":[36,44],"circuit,":[37],"reference":[40],"PLL.":[41,58],"A":[42],"detects":[46],"the":[47,53],"instantaneous":[48],"bit":[49],"rate":[50],"switches":[52],"was":[61],"designed":[62],"in":[63],"25-GHz":[65],"f/sub":[66],"T/":[67],"Si-bipolar":[68],"transistor":[69],"array":[70],"dissipates":[72],"680":[73],"mW":[74],"from":[75],"-5":[76],"V":[77],"supply":[78],"voltage.":[79],"Jitter":[80],"performance":[81],"is":[82],"compliant":[83],"with":[84],"SDH/SONET":[85],"specifications.":[86]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-11-04T10:54:05.112534","created_date":"2016-06-24T00:00:00"}
