{"id":"https://openalex.org/W2142811052","doi":null,"title":"Multiple Mini-Processor Computer Structures,","display_name":"Multiple Mini-Processor Computer Structures,","publication_year":1973,"publication_date":"1973-08-01","ids":{"openalex":"https://openalex.org/W2142811052","mag":"2142811052"},"language":"en","primary_location":{"id":"pmh:ADA004185","doi":null,"is_oa":false,"landing_page_url":"http://oai.dtic.mil/oai/oai?&amp;verb=getRecord&amp;metadataPrefix=html&amp;identifier=ADA004185","pdf_url":null,"source":{"id":"https://openalex.org/S4406923043","display_name":"Defense Technical Information Center (DTIC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"DTIC AND NTIS","raw_type":"Text"},"volume":null,"type":"article","is_traditional":true,"indexed_in":[],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5070771949","display_name":"Firmo Freire","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Firmo Freire","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":["https://openalex.org/A5070771949"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.0,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.5541999936103821,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.5541999936103821,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.42329999804496765,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.003700000001117587,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-architecture","display_name":"computer architecture","score":0.5720000267028809},{"id":"https://openalex.org/keywords/processor-design","display_name":"processor design","score":0.4959999918937683},{"id":"https://openalex.org/keywords/simulation-study","display_name":"simulation study","score":0.5920000076293945},{"id":"https://openalex.org/keywords/feasibility-study","display_name":"feasibility study","score":0.6579999923706055}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6328980922698975},{"id":"https://openalex.org/C121684516","wikidata":"https://www.wikidata.org/wiki/Q7600677","display_name":"Computer graphics (images)","level":1,"score":0.34354859590530396}],"mesh":[],"locations_count":2,"locations":[{"id":"pmh:ADA004185","doi":null,"is_oa":false,"landing_page_url":"http://oai.dtic.mil/oai/oai?&amp;verb=getRecord&amp;metadataPrefix=html&amp;identifier=ADA004185","pdf_url":null,"source":{"id":"https://openalex.org/S4406923043","display_name":"Defense Technical Information Center (DTIC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"DTIC AND NTIS","raw_type":"Text"},{"id":"mag:2142811052","doi":null,"is_oa":false,"landing_page_url":"https://apps.dtic.mil/sti/pdfs/ADA004185.pdf","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W851822676","https://openalex.org/W4230076130","https://openalex.org/W7043372273","https://openalex.org/W249617084","https://openalex.org/W2585364417","https://openalex.org/W2913267467","https://openalex.org/W405824870","https://openalex.org/W7099239930","https://openalex.org/W198865841","https://openalex.org/W2051147755"],"abstract_inverted_index":{"This":[0],"paper":[1],"reports":[2],"on":[3],"a":[4],"detailed":[5],"simulation":[6],"study":[7],"of":[8,11],"the":[9],"feasibility":[10],"two":[12],"different":[13],"designs":[14],"for":[15],"multiple":[16],"mini-processor":[17],"computer":[18],"structures.":[19]},"counts_by_year":[],"updated_date":"2026-08-26T07:47:46.906454","created_date":"2016-06-24T00:00:00"}
