{"id":"https://openalex.org/W2142000962","doi":"https://doi.org/10.1109/tcad.2009.2034343","title":"Effective Corner-Based Techniques for Variation-Aware IC Timing Verification","display_name":"Effective Corner-Based Techniques for Variation-Aware IC Timing Verification","publication_year":2009,"publication_date":"2009-12-24","ids":{"openalex":"https://openalex.org/W2142000962","doi":"https://doi.org/10.1109/tcad.2009.2034343","mag":"2142000962"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2009.2034343","doi":"https://doi.org/10.1109/tcad.2009.2034343","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2009.2034343","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["ccf-a","cwts-core","dongbi-a","jufo-2","norway-1","poland-100","russia-white-list-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"volume":null,"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074463063","display_name":"Lu\u00eds Guerra e Silva","orcid":"https://orcid.org/0000-0001-5761-0131","observed_orcids":["https://orcid.org/0000-0001-5761-0131"]},"institutions":[{"id":"https://openalex.org/I4405264366","display_name":"Universidade T\u00e9cnica de Lisboa","ror":"https://ror.org/01qc02b16","country_code":"PT","type":"education","lineage":["https://openalex.org/I141596103","https://openalex.org/I4405264366"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Luis Guerra e Silva","raw_affiliation_strings":["Department of Information Systems and Computer Science, Instituto Superior \u00e9cnico, Technical University of Lisbon, Lisboa, Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Information Systems and Computer Science, Instituto Superior \u00e9cnico, Technical University of Lisbon, Lisboa, Portugal","institution_ids":["https://openalex.org/I4405264366"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060124540","display_name":"Joel R. Phillips","orcid":"https://orcid.org/0000-0002-3437-425X","observed_orcids":["https://orcid.org/0000-0002-3437-425X"]},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Joel Phillips","raw_affiliation_strings":["Cadence Research Laboratories, Cadence Design Systems, Berkeley, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cadence Research Laboratories, Cadence Design Systems, Berkeley, CA, USA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052100713","display_name":"Luis Miguel Silveira","orcid":"https://orcid.org/0000-0003-3542-229X","observed_orcids":["https://orcid.org/0000-0003-3542-229X"]},"institutions":[{"id":"https://openalex.org/I4387152517","display_name":"Instituto Superior T\u00e9cnico","ror":"https://ror.org/03db2by73","country_code":"PT","type":"education","lineage":["https://openalex.org/I141596103","https://openalex.org/I4387152517"]},{"id":"https://openalex.org/I4405264366","display_name":"Universidade T\u00e9cnica de Lisboa","ror":"https://ror.org/01qc02b16","country_code":"PT","type":"education","lineage":["https://openalex.org/I141596103","https://openalex.org/I4405264366"]},{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["PT","US"],"is_corresponding":false,"raw_author_name":"L. Miguel Silveira","raw_affiliation_strings":["Cadence Research Laboratories, Cadence Design Systems, Berkeley, CA, USA","Department of Electrical and Computer Engineering, Instituto Superior T\u00e9cnico, Technical University of Lisbon, Lisboa, Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cadence Research Laboratories, Cadence Design Systems, Berkeley, CA, USA","institution_ids":["https://openalex.org/I66217453"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Instituto Superior T\u00e9cnico, Technical University of Lisbon, Lisboa, Portugal","institution_ids":["https://openalex.org/I4387152517","https://openalex.org/I4405264366"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":2645,"currency":"USD","value_usd":2645},"apc_paid":null,"fwci":1.0578,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.801695,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"29","issue":"1","first_page":"157","last_page":"162"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9125999808311462,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9125999808311462,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.04910000041127205,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.019899999722838402,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/process-variation","display_name":"process variation","score":0.7080000042915344},{"id":"https://openalex.org/keywords/combinational-circuits","display_name":"combinational circuits","score":0.7269999980926514},{"id":"https://openalex.org/keywords/sequential-circuits","display_name":"sequential circuits","score":0.9589999914169312},{"id":"https://openalex.org/keywords/digital-integrated-circuits","display_name":"digital integrated circuits","score":0.7080000042915344},{"id":"https://openalex.org/keywords/timing-variability","display_name":"timing variability","score":0.6060000061988831},{"id":"https://openalex.org/keywords/design-for-variability","display_name":"design for variability","score":0.3179999887943268}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6344508528709412},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.6250472664833069},{"id":"https://openalex.org/C2780428219","wikidata":"https://www.wikidata.org/wiki/Q16952335","display_name":"Cover (algebra)","level":2,"score":0.6229103803634644},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.597603976726532},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.5702060461044312},{"id":"https://openalex.org/C2778334786","wikidata":"https://www.wikidata.org/wiki/Q1586270","display_name":"Variation (astronomy)","level":2,"score":0.5474668741226196},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4807005524635315},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.47279495000839233},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.47197943925857544},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.4523400664329529},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4403519928455353},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.43819817900657654},{"id":"https://openalex.org/C139676723","wikidata":"https://www.wikidata.org/wiki/Q1193832","display_name":"Sign (mathematics)","level":2,"score":0.425251841545105},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.32481950521469116},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.20657533407211304},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1909348964691162},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.16789773106575012},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15247488021850586},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.07456481456756592},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C44870925","wikidata":"https://www.wikidata.org/wiki/Q37547","display_name":"Astrophysics","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2009.2034343","doi":"https://doi.org/10.1109/tcad.2009.2034343","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2009.2034343","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["ccf-a","cwts-core","dongbi-a","jufo-2","norway-1","poland-100","russia-white-list-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.428600013256073}],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1966741973","https://openalex.org/W1978543128","https://openalex.org/W2047518460","https://openalex.org/W2062907832","https://openalex.org/W2121845874","https://openalex.org/W2126564504","https://openalex.org/W2144931885","https://openalex.org/W2148507902","https://openalex.org/W2163262735","https://openalex.org/W2296319761","https://openalex.org/W2544718775","https://openalex.org/W4237955880","https://openalex.org/W4248062893"],"related_works":["https://openalex.org/W2148507902","https://openalex.org/W2121845874","https://openalex.org/W2461865212","https://openalex.org/W7100689560","https://openalex.org/W2532344226","https://openalex.org/W3144895071","https://openalex.org/W2080533153","https://openalex.org/W2544718775","https://openalex.org/W7096335943","https://openalex.org/W7099879904"],"abstract_inverted_index":{"Traditional":[0],"integrated":[1,98],"circuit":[2],"timing":[3,117],"sign-off":[4],"consists":[5],"of":[6,13,17,36,61,93,111],"verifying":[7],"a":[8,11],"design":[9],"for":[10,87,116],"set":[12],"carefully":[14],"chosen":[15,31],"combinations":[16],"process":[18,39,121],"and":[19,38,41,49,90,95,108],"operating":[20,50],"parameter":[21],"extremes,":[22],"referred":[23],"to":[24,44,57,64,74,120],"as":[25],"corners.":[26],"Such":[27],"corners":[28,92],"are":[29,42],"usually":[30],"based":[32],"on":[33],"the":[34,46,59,103],"knowledge":[35],"designers":[37],"engineers,":[40],"expected":[43],"cover":[45],"worst-case":[47],"fabrication":[48],"scenarios.":[51],"With":[52],"increasingly":[53],"more":[54,70],"detailed":[55],"attention":[56],"variability,":[58],"number":[60],"potential":[62],"conditions":[63,113],"examine":[65],"can":[66],"be":[67],"exponentially":[68],"large,":[69],"than":[71],"is":[72],"possible":[73],"handle":[75],"with":[76],"straightforward":[77],"exhaustive":[78],"analysis.":[79],"This":[80],"paper":[81],"presents":[82],"efficient":[83,107],"yet":[84],"exact":[85],"techniques":[86,105],"computing":[88],"worst-delay":[89],"worst-slack":[91],"combinational":[94],"sequential":[96],"digital":[97],"circuits.":[99],"Results":[100],"show":[101],"that":[102],"proposed":[104],"enable":[106],"accurate":[109],"detection":[110],"failing":[112],"while":[114],"accounting":[115],"variability":[118],"due":[119],"variations.":[122]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2026-10-16T09:59:22.235173","created_date":"2016-06-24T00:00:00"}
