{"id":"https://openalex.org/W2140877331","doi":"https://doi.org/10.1109/glsv.1991.143995","title":"HADES-high-level architecture development and exploration system","display_name":"HADES-high-level architecture development and exploration system","publication_year":2002,"publication_date":"2002-12-10","ids":{"openalex":"https://openalex.org/W2140877331","doi":"https://doi.org/10.1109/glsv.1991.143995","mag":"2140877331"},"language":"en","primary_location":{"id":"doi:10.1109/glsv.1991.143995","doi":"https://doi.org/10.1109/glsv.1991.143995","is_oa":false,"landing_page_url":"https://doi.org/10.1109/glsv.1991.143995","pdf_url":null,"source":{"id":"https://openalex.org/S4363608736","display_name":"ACM Great Lakes Symposium on VLSI (GLSVLSI)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020161854","display_name":"P. Poechmueller","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technische Universit\u00e4t Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"P. Poechmueller","raw_affiliation_strings":["Institute of Microelectronic Systems, Darmstadt University of Technology, Darmstadt, Germany","Inst. of Microelectron. Systems, Darmstadt Univ. of Technol., Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronic Systems, Darmstadt University of Technology, Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]},{"raw_affiliation_string":"Inst. of Microelectron. Systems, Darmstadt Univ. of Technol., Germany","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056996417","display_name":"M. Held","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technische Universit\u00e4t Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"M. Held","raw_affiliation_strings":["Institute of Microelectronic Systems, Darmstadt University of Technology, Darmstadt, Germany","Inst. of Microelectron. Systems, Darmstadt Univ. of Technol., Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronic Systems, Darmstadt University of Technology, Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]},{"raw_affiliation_string":"Inst. of Microelectron. Systems, Darmstadt Univ. of Technol., Germany","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059285190","display_name":"Norbert Wehn","orcid":"https://orcid.org/0000-0002-9010-086X","observed_orcids":["https://orcid.org/0000-0002-9010-086X"]},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technische Universit\u00e4t Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"N. Wehn","raw_affiliation_strings":["Institute of Microelectronic Systems, Darmstadt University of Technology, Darmstadt, Germany","Inst. of Microelectron. Systems, Darmstadt Univ. of Technol., Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronic Systems, Darmstadt University of Technology, Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]},{"raw_affiliation_string":"Inst. of Microelectron. Systems, Darmstadt Univ. of Technol., Germany","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002162776","display_name":"Manfred Glesner","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technische Universit\u00e4t Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"M. Glesner","raw_affiliation_strings":["Institute of Microelectronic Systems, Darmstadt University of Technology, Darmstadt, Germany","Inst. of Microelectron. Systems, Darmstadt Univ. of Technol., Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronic Systems, Darmstadt University of Technology, Darmstadt, Germany","institution_ids":["https://openalex.org/I31512782"]},{"raw_affiliation_string":"Inst. of Microelectron. Systems, Darmstadt Univ. of Technol., Germany","institution_ids":["https://openalex.org/I31512782"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I31512782"],"apc_list":null,"apc_paid":null,"fwci":1.2075,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.77239499,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"342","last_page":"343"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.0013000000035390258,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.00019999999494757503,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"high-level synthesis","score":0.7440000176429749},{"id":"https://openalex.org/keywords/behavioural-synthesis","display_name":"behavioural synthesis","score":0.8050000071525574},{"id":"https://openalex.org/keywords/loop-unrolling","display_name":"loop unrolling","score":0.9570000171661377},{"id":"https://openalex.org/keywords/parallelization","display_name":"parallelization","score":0.984000027179718},{"id":"https://openalex.org/keywords/genetic-algorithm","display_name":"genetic algorithm","score":0.6449999809265137},{"id":"https://openalex.org/keywords/structural-synthesis","display_name":"structural synthesis","score":0.9660000205039978},{"id":"https://openalex.org/keywords/layout-synthesis","display_name":"layout synthesis","score":0.7329999804496765},{"id":"https://openalex.org/keywords/hardware-design-automation","display_name":"hardware design automation","score":0.3479999899864197}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7969531416893005},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.7806370258331299},{"id":"https://openalex.org/C76970557","wikidata":"https://www.wikidata.org/wiki/Q1869750","display_name":"Loop unrolling","level":3,"score":0.7373683452606201},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.6192659735679626},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.5020852088928223},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.5003781318664551},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4752887487411499},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.463365763425827},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.4316169321537018},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4285024404525757},{"id":"https://openalex.org/C27458966","wikidata":"https://www.wikidata.org/wiki/Q1187693","display_name":"Control flow graph","level":2,"score":0.4170885384082794},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.38902053236961365},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.18246150016784668},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.14734143018722534},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/glsv.1991.143995","doi":"https://doi.org/10.1109/glsv.1991.143995","is_oa":false,"landing_page_url":"https://doi.org/10.1109/glsv.1991.143995","pdf_url":null,"source":{"id":"https://openalex.org/S4363608736","display_name":"ACM Great Lakes Symposium on VLSI (GLSVLSI)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"[1991] Proceedings. First Great Lakes Symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1520573145","https://openalex.org/W2087376924","https://openalex.org/W2093842169","https://openalex.org/W2146169157","https://openalex.org/W3023540311","https://openalex.org/W4252239987"],"related_works":["https://openalex.org/W2184191074","https://openalex.org/W1964556228","https://openalex.org/W1553329297","https://openalex.org/W2096134444","https://openalex.org/W1584211151","https://openalex.org/W7098362403","https://openalex.org/W422457019","https://openalex.org/W7100219069","https://openalex.org/W2497068368","https://openalex.org/W2168010321"],"abstract_inverted_index":{"The":[0,19,32],"authors":[1],"propose":[2],"a":[3,24,52],"new":[4],"approach":[5],"to":[6,72],"high":[7],"level":[8],"behavioural":[9,33],"synthesis":[10,34,58,69],"starting":[11],"from":[12],"an":[13,59],"algorithmic":[14],"description":[15],"in":[16],"Hardware":[17],"C.":[18],"algorithm":[20],"is":[21,49,66,70],"compiled":[22],"into":[23],"corresponding":[25],"data/control":[26],"flow":[27],"graph":[28],"including":[29],"several":[30],"optimizations.":[31],"part":[35],"of":[36],"the":[37,47,79],"system":[38],"performs":[39],"transformations":[40],"like":[41,78],"loop":[42],"unrolling,":[43],"parallelization,":[44],"etc.,":[45],"whereby":[46],"user":[48],"supported":[50],"through":[51],"feedback":[53],"loop.":[54],"For":[55],"final":[56],"structural":[57],"advanced":[60],"tool":[61],"based":[62],"on":[63],"genetic":[64],"algorithms":[65],"provided.":[67],"Layout":[68],"assumed":[71],"be":[73],"performed":[74],"by":[75],"available":[76],"tools":[77],"GENESIL":[80],"silicon":[81],"compiler.>":[82]},"counts_by_year":[],"updated_date":"2026-11-04T10:54:05.112534","created_date":"2016-06-24T00:00:00"}