{"id":"https://openalex.org/W2139703237","doi":"https://doi.org/10.1109/te.2005.853069","title":"A Framework for Teaching Real-Time Digital Signal Processing With Field-Programmable Gate Arrays","display_name":"A Framework for Teaching Real-Time Digital Signal Processing With Field-Programmable Gate Arrays","publication_year":2005,"publication_date":"2005-08-01","ids":{"openalex":"https://openalex.org/W2139703237","doi":"https://doi.org/10.1109/te.2005.853069","mag":"2139703237"},"language":"en","primary_location":{"id":"doi:10.1109/te.2005.853069","doi":"https://doi.org/10.1109/te.2005.853069","is_oa":false,"landing_page_url":"https://doi.org/10.1109/te.2005.853069","pdf_url":null,"source":{"id":"https://openalex.org/S207741693","display_name":"IEEE Transactions on Education","issn_l":"0018-9359","issn":["0018-9359","1557-9638"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","erih-plus","jufo-1","norway-1"],"host_organization":"https://openalex.org/P4310322189","host_organization_name":"IEEE Education Society","host_organization_lineage":["https://openalex.org/P4310322189","https://openalex.org/P4310319808"],"host_organization_lineage_names":["IEEE Education Society","Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Education","raw_type":"journal-article"},"volume":null,"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5013069164","display_name":"Tyson S. Hall","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I175938002","display_name":"Southern Adventist University","ror":"https://ror.org/04xafps82","country_code":"US","type":"education","lineage":["https://openalex.org/I175938002"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"T.S. Hall","raw_affiliation_strings":["School of Computing, Southern Adventist University, Collegedale, TN, USA","Sch. of Comput., Southern Adventist Univ., Collegedale, TN, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computing, Southern Adventist University, Collegedale, TN, USA","institution_ids":["https://openalex.org/I175938002"]},{"raw_affiliation_string":"Sch. of Comput., Southern Adventist Univ., Collegedale, TN, USA","institution_ids":["https://openalex.org/I175938002"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5033437141","display_name":"David V. Anderson","orcid":"https://orcid.org/0000-0002-8571-4613","observed_orcids":["https://orcid.org/0000-0002-8571-4613"]},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D.V. Anderson","raw_affiliation_strings":["Georgia Institute of Technology, Atlanta, GA, USA","Georgia Institute of Technology Atlanta, GA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"Georgia Institute of Technology Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":2645,"currency":"USD","value_usd":2645},"apc_paid":null,"fwci":76.5748,"has_fulltext":false,"cited_by_count":28,"citation_normalized_percentile":{"value":0.99797728,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"48","issue":"3","first_page":"551","last_page":"558"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T13682","display_name":"Engineering Education and Pedagogy","score":0.5839999914169312,"subfield":{"id":"https://openalex.org/subfields/2216","display_name":"Architecture"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T13682","display_name":"Engineering Education and Pedagogy","score":0.5839999914169312,"subfield":{"id":"https://openalex.org/subfields/2216","display_name":"Architecture"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11283","display_name":"Experimental Learning in Engineering","score":0.2583000063896179,"subfield":{"id":"https://openalex.org/subfields/2214","display_name":"Media Technology"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":0.10999999940395355,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/digital-signal-processing-education","display_name":"digital signal processing education","score":0.8790000081062317},{"id":"https://openalex.org/keywords/fpga","display_name":"FPGA","score":0.9829999804496765},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.9509999752044678},{"id":"https://openalex.org/keywords/hardware-design","display_name":"hardware design","score":0.5759999752044678},{"id":"https://openalex.org/keywords/hardware-synthesis","display_name":"hardware synthesis","score":0.5519999861717224},{"id":"https://openalex.org/keywords/hardware-prototyping","display_name":"hardware prototyping","score":0.640999972820282},{"id":"https://openalex.org/keywords/finite-precision-effects","display_name":"finite precision effects","score":0.8140000104904175},{"id":"https://openalex.org/keywords/parallel-implementation","display_name":"parallel implementation","score":0.9559999704360962},{"id":"https://openalex.org/keywords/pedagogical-framework","display_name":"pedagogical framework","score":0.7239999771118164}],"concepts":[{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.8306629657745361},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.7546359300613403},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7131097912788391},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6986255049705505},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.6357530355453491},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5794340968132019},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4885424077510834},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.4821986258029938},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4532214403152466},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.4459574222564697},{"id":"https://openalex.org/C153083717","wikidata":"https://www.wikidata.org/wiki/Q6535263","display_name":"Leverage (statistics)","level":2,"score":0.43802961707115173},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.43163660168647766},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.4226316809654236},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3528977334499359},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3177303075790405},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2102389931678772},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.08284276723861694},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/te.2005.853069","doi":"https://doi.org/10.1109/te.2005.853069","is_oa":false,"landing_page_url":"https://doi.org/10.1109/te.2005.853069","pdf_url":null,"source":{"id":"https://openalex.org/S207741693","display_name":"IEEE Transactions on Education","issn_l":"0018-9359","issn":["0018-9359","1557-9638"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","erih-plus","jufo-1","norway-1"],"host_organization":"https://openalex.org/P4310322189","host_organization_name":"IEEE Education Society","host_organization_lineage":["https://openalex.org/P4310322189","https://openalex.org/P4310319808"],"host_organization_lineage_names":["IEEE Education Society","Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Education","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.409.4794","doi":null,"is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.409.4794","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.hallway.us/~tyson/downloads/tred_2005.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.932.5347","doi":null,"is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.932.5347","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://knowledge.e.southern.edu/cgi/viewcontent.cgi?article%3D1006%26context%3Dfacworks_comp","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Quality education","id":"https://metadata.un.org/sdg/4","score":0.975600004196167}],"sustainable_development_goals_aurora":[{"display_name":"Quality education","id":"https://metadata.un.org/sdg/4","score":0.5099999904632568}],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W96980196","https://openalex.org/W1519267616","https://openalex.org/W1526289540","https://openalex.org/W1838212059","https://openalex.org/W1998729624","https://openalex.org/W2004904945","https://openalex.org/W2095603848","https://openalex.org/W2115543692","https://openalex.org/W2115954667","https://openalex.org/W2116339080","https://openalex.org/W2120245481","https://openalex.org/W2147688363","https://openalex.org/W2171918054","https://openalex.org/W2181519520","https://openalex.org/W2534657550","https://openalex.org/W2535194716","https://openalex.org/W2541398547","https://openalex.org/W2541502040","https://openalex.org/W2544478735","https://openalex.org/W2625599568"],"related_works":["https://openalex.org/W2384838054","https://openalex.org/W2363829830","https://openalex.org/W1843355381","https://openalex.org/W1988777083","https://openalex.org/W1530924151","https://openalex.org/W2370873755","https://openalex.org/W9221892","https://openalex.org/W2534549730","https://openalex.org/W1873290954","https://openalex.org/W2167874369"],"abstract_inverted_index":{"Many":[0],"curricula":[1],"include":[2],"separate":[3],"classes":[4],"in":[5,95],"both":[6],"digital":[7,70],"signal":[8,71,133],"processing":[9,72,134],"(DSP)":[10],"theory":[11,58],"and":[12,59,68,88,120,124,141],"very":[13],"high-speed":[14],"integrated":[15],"circuit":[16],"hardware":[17,41,61,76,93],"description":[18],"language":[19],"(VHDL)":[20],"modeling;":[21],"however,":[22],"there":[23],"are":[24,127],"few":[25],"opportunities":[26],"given":[27],"to":[28,30,64,103,129],"students":[29,50,102],"combine":[31],"these":[32],"two":[33],"skills":[34],"into":[35,108],"a":[36,86,96,109],"working":[37],"knowledge":[38,55,107],"of":[39,56,91,113,132],"DSP":[40,57],"design.":[42],"A":[43],"pedagogical":[44],"framework":[45,100],"has":[46],"been":[47],"developed":[48],"whereby":[49],"can":[51],"leverage":[52],"their":[53,105],"previous":[54,106],"VHDL":[60],"design":[62,116],"techniques":[63],"design,":[65,135],"simulate,":[66],"synthesize,":[67],"test":[69],"systems.":[73],"The":[74],"synthesized":[75],"is":[77],"implemented":[78],"on":[79],"field-programmable":[80],"gate":[81],"arrays":[82],"(FPGAs),":[83],"which":[84],"provide":[85],"fast":[87],"cost-effective":[89],"way":[90],"prototyping":[92],"systems":[94],"laboratory":[97],"environment.":[98],"This":[99],"allows":[101],"expand":[104],"more":[110],"complete":[111],"understanding":[112],"the":[114],"entire":[115],"process":[117],"from":[118],"specification":[119],"simulation":[121],"through":[122],"synthesis":[123],"verification.":[125],"Students":[126],"exposed":[128],"different":[130],"aspects":[131],"including":[136],"finite":[137],"precision,":[138],"parallel":[139],"implementation,":[140],"implementation":[142],"cost":[143],"tradeoffs.":[144]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":1}],"updated_date":"2026-08-26T07:47:46.906454","created_date":"2025-10-10T00:00:00"}