{"id":"https://openalex.org/W2139557356","doi":"https://doi.org/10.1109/iscas.2006.1693233","title":"Side Channel Analysis Resistant Design Flow","display_name":"Side Channel Analysis Resistant Design Flow","publication_year":2006,"publication_date":"2006-09-22","ids":{"openalex":"https://openalex.org/W2139557356","doi":"https://doi.org/10.1109/iscas.2006.1693233","mag":"2139557356"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2006.1693233","doi":"https://doi.org/10.1109/iscas.2006.1693233","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1693233","pdf_url":null,"source":{"id":"https://openalex.org/S4393914142","display_name":"IEEE International Symposium on Circuits and Systems proceedings","issn_l":"0271-4302","issn":["0271-4302"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":["jufo-1","norway-1"],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054583230","display_name":"Manfred Aigner","orcid":"https://orcid.org/0000-0001-8723-4966","observed_orcids":["https://orcid.org/0000-0001-8723-4966"]},"institutions":[{"id":"https://openalex.org/I4092182","display_name":"Graz University of Technology","ror":"https://ror.org/00d7xrm67","country_code":"AT","type":"education","lineage":["https://openalex.org/I4092182"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"M. Aigner","raw_affiliation_strings":["IAIK - Institute for Applied Information Processing and Communications, Graz University of Technology, Graz, Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IAIK - Institute for Applied Information Processing and Communications, Graz University of Technology, Graz, Austria","institution_ids":["https://openalex.org/I4092182"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015437576","display_name":"Stefan Mangard","orcid":"https://orcid.org/0000-0001-9650-8041","observed_orcids":["https://orcid.org/0000-0001-9650-8041"]},"institutions":[{"id":"https://openalex.org/I4092182","display_name":"Graz University of Technology","ror":"https://ror.org/00d7xrm67","country_code":"AT","type":"education","lineage":["https://openalex.org/I4092182"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"S. Mangard","raw_affiliation_strings":["IAIK - Institute for Applied Information Processing and Communications, Graz University of Technology, Graz, Austria","IAIK-Institute of Applied Information Processing and Communications, Graz, Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IAIK - Institute for Applied Information Processing and Communications, Graz University of Technology, Graz, Austria","institution_ids":["https://openalex.org/I4092182"]},{"raw_affiliation_string":"IAIK-Institute of Applied Information Processing and Communications, Graz, Austria","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045257843","display_name":"Francesco Menichelli","orcid":"https://orcid.org/0000-0002-8453-6536","observed_orcids":["https://orcid.org/0000-0002-8453-6536"]},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"F. Menichelli","raw_affiliation_strings":["DIE - Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma \u201cLa Sapienza\u201d, Roma, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DIE - Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma \u201cLa Sapienza\u201d, Roma, Italy","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066580663","display_name":"Renato Menicocci","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"R. Menicocci","raw_affiliation_strings":["DIE - Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma \u201cLa Sapienza\u201d, Roma, Italy","IAIK-Institute of Applied Information Processing and Communications, Graz, Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DIE - Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma \u201cLa Sapienza\u201d, Roma, Italy","institution_ids":["https://openalex.org/I861853513"]},{"raw_affiliation_string":"IAIK-Institute of Applied Information Processing and Communications, Graz, Austria","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067054447","display_name":"Mauro Olivieri","orcid":"https://orcid.org/0000-0002-0214-9904","observed_orcids":["https://orcid.org/0000-0002-0214-9904"]},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Olivieri","raw_affiliation_strings":["DIE - Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma \u201cLa Sapienza\u201d, Roma, Italy","IAIK-Institute of Applied Information Processing and Communications, Graz, Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DIE - Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma \u201cLa Sapienza\u201d, Roma, Italy","institution_ids":["https://openalex.org/I861853513"]},{"raw_affiliation_string":"IAIK-Institute of Applied Information Processing and Communications, Graz, Austria","institution_ids":[]}]},{"author_position":"middle","author":{"id":null,"display_name":"T. Popp","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4092182","display_name":"Graz University of Technology","ror":"https://ror.org/00d7xrm67","country_code":"AT","type":"education","lineage":["https://openalex.org/I4092182"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"T. Popp","raw_affiliation_strings":["IAIK - Institute for Applied Information Processing and Communications, Graz University of Technology, Graz, Austria","IAIK-Institute of Applied Information Processing and Communications, Graz, Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IAIK - Institute for Applied Information Processing and Communications, Graz University of Technology, Graz, Austria","institution_ids":["https://openalex.org/I4092182"]},{"raw_affiliation_string":"IAIK-Institute of Applied Information Processing and Communications, Graz, Austria","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010336494","display_name":"Giuseppe Scotti","orcid":"https://orcid.org/0000-0002-5650-8212","observed_orcids":["https://orcid.org/0000-0002-5650-8212"]},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"G. Scotti","raw_affiliation_strings":["DIE - Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma \u201cLa Sapienza\u201d, Roma, Italy","IAIK-Institute of Applied Information Processing and Communications, Graz, Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DIE - Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma \u201cLa Sapienza\u201d, Roma, Italy","institution_ids":["https://openalex.org/I861853513"]},{"raw_affiliation_string":"IAIK-Institute of Applied Information Processing and Communications, Graz, Austria","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068452963","display_name":"Alessandro Trifiletti","orcid":"https://orcid.org/0000-0001-6231-4273","observed_orcids":["https://orcid.org/0000-0001-6231-4273"]},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"A. Trifiletti","raw_affiliation_strings":["DIE - Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma \u201cLa Sapienza\u201d, Roma, Italy","IAIK-Institute of Applied Information Processing and Communications, Graz, Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DIE - Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma \u201cLa Sapienza\u201d, Roma, Italy","institution_ids":["https://openalex.org/I861853513"]},{"raw_affiliation_string":"IAIK-Institute of Applied Information Processing and Communications, Graz, Austria","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.2289,"has_fulltext":false,"cited_by_count":27,"citation_normalized_percentile":{"value":0.87941347,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":87,"max":97},"biblio":{"volume":"2779","issue":null,"first_page":"2909","last_page":"2912"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9731000065803528,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9731000065803528,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.023099999874830246,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11693","display_name":"Cryptography and Residue Arithmetic","score":0.0007999999797903001,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/side-channel-attacks","display_name":"side-channel attacks","score":0.9950000047683716},{"id":"https://openalex.org/keywords/side-channel-resistance","display_name":"side-channel attack resistance","score":0.7799999713897705},{"id":"https://openalex.org/keywords/secure-hardware-design","display_name":"secure hardware design","score":0.6470000147819519},{"id":"https://openalex.org/keywords/cryptographic-hardware","display_name":"cryptographic hardware","score":0.7710000276565552},{"id":"https://openalex.org/keywords/design-flow","display_name":"design flow","score":0.6779999732971191}],"concepts":[{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.7933729887008667},{"id":"https://openalex.org/C49289754","wikidata":"https://www.wikidata.org/wiki/Q2267081","display_name":"Side channel attack","level":3,"score":0.7906433343887329},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6951494812965393},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.6006315350532532},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.5515657067298889},{"id":"https://openalex.org/C178489894","wikidata":"https://www.wikidata.org/wiki/Q8789","display_name":"Cryptography","level":2,"score":0.5483414530754089},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.5403819680213928},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5198019742965698},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.49846959114074707},{"id":"https://openalex.org/C2982740150","wikidata":"https://www.wikidata.org/wiki/Q5249230","display_name":"Design cycle","level":2,"score":0.4867572784423828},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.45061057806015015},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4498620331287384},{"id":"https://openalex.org/C38349280","wikidata":"https://www.wikidata.org/wiki/Q1434290","display_name":"Flow (mathematics)","level":2,"score":0.4463196098804474},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.41552963852882385},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.4155064821243286},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4117690324783325},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.3334019184112549},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.2385169267654419},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22732976078987122},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.16257598996162415},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.15423601865768433},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11888468265533447},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/iscas.2006.1693233","doi":"https://doi.org/10.1109/iscas.2006.1693233","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1693233","pdf_url":null,"source":{"id":"https://openalex.org/S4393914142","display_name":"IEEE International Symposium on Circuits and Systems proceedings","issn_l":"0271-4302","issn":["0271-4302"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":["jufo-1","norway-1"],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:iris.uniroma1.it:11573/462623","doi":null,"is_oa":false,"landing_page_url":"http://hdl.handle.net/11573/462623","pdf_url":null,"source":{"id":"https://openalex.org/S4377196107","display_name":"IRIS Research product catalog (Sapienza University of Rome)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:oai:iris.uniroma1.it:11573/893891","doi":null,"is_oa":false,"landing_page_url":"http://hdl.handle.net/11573/893891","pdf_url":null,"source":{"id":"https://openalex.org/S4377196107","display_name":"IRIS Research product catalog (Sapienza University of Rome)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1506423869","https://openalex.org/W1538105527","https://openalex.org/W1552623947","https://openalex.org/W1575446397","https://openalex.org/W2008390649","https://openalex.org/W2099086025","https://openalex.org/W2099724084","https://openalex.org/W2101922456","https://openalex.org/W2133707980","https://openalex.org/W2144630005","https://openalex.org/W2154909745","https://openalex.org/W2164584813","https://openalex.org/W2406868528","https://openalex.org/W4231098049"],"related_works":["https://openalex.org/W2108742901","https://openalex.org/W2064900563","https://openalex.org/W2156494642","https://openalex.org/W2144765857","https://openalex.org/W2593479102","https://openalex.org/W2735090663","https://openalex.org/W3191497668","https://openalex.org/W2563615640","https://openalex.org/W7100367435","https://openalex.org/W3131564815"],"abstract_inverted_index":{"The":[0,18],"threat":[1],"of":[2,7,50,55,67,81],"side-channel":[3,36],"attacks":[4],"(SCA)":[5],"is":[6,87,105],"crucial":[8],"importance":[9],"when":[10],"designing":[11,35],"systems":[12,52],"with":[13],"cryptographic":[14],"hardware":[15],"or":[16],"software.":[17],"FP6-funded":[19],"project":[20,57],"SCARD":[21,86,96],"enhances":[22],"the":[23,48,56,75,78,92,101],"typical":[24],"micro-chip":[25],"design":[26,65,76,103],"flow":[27,104],"in":[28,71,88],"order":[29,72],"to":[30,73],"provide":[31],"a":[32,95],"means":[33],"for":[34,47,63,77],"resistant":[37],"circuits":[38],"and":[39,44,83],"systems.":[40],"Appropriate":[41],"SCA-simulation":[42],"tools":[43],"SCA":[45],"analysis":[46],"designer":[49],"secure":[51,82],"are":[53],"part":[54],"goals.":[58],"We":[59],"consider":[60],"these":[61],"enhancements":[62],"traditional":[64],"flows":[66],"micro-chips":[68],"as":[69],"necessary":[70],"enable":[74],"next":[79],"generation":[80],"dependable":[84],"devices.":[85],"its":[89],"final":[90,93],"phase,":[91],"result":[94],"chip":[97],"designed":[98],"by":[99],"using":[100],"developed":[102],"currently":[106],"implemented":[107]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":2}],"updated_date":"2026-10-30T12:39:25.321706","created_date":"2016-06-24T00:00:00"}