{"id":"https://openalex.org/W2139151515","doi":"https://doi.org/10.1109/vlsic.1998.688098","title":"A sophisticated bit-by-bit verifying scheme for NAND EEPROMs","display_name":"A sophisticated bit-by-bit verifying scheme for NAND EEPROMs","publication_year":2002,"publication_date":"2002-11-27","ids":{"openalex":"https://openalex.org/W2139151515","doi":"https://doi.org/10.1109/vlsic.1998.688098","mag":"2139151515"},"language":"en","primary_location":{"id":"doi:10.1109/vlsic.1998.688098","doi":"https://doi.org/10.1109/vlsic.1998.688098","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsic.1998.688098","pdf_url":null,"source":{"id":"https://openalex.org/S4393918263","display_name":"Symposium on VLSI Circuits","issn_l":"2166-9600","issn":["2166-9600"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":["jufo-1"],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075738265","display_name":"Koji Sakui","orcid":"https://orcid.org/0000-0003-2086-4802","observed_orcids":["https://orcid.org/0000-0003-2086-4802"]},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"K. Sakui","raw_affiliation_strings":["ULSI Device Engineering Laboratory, Toshiba Corporation, Yokohama, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ULSI Device Engineering Laboratory, Toshiba Corporation, Yokohama, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025468532","display_name":"Kazushige Kanda","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"K. Kanda","raw_affiliation_strings":["ULSI Device Engineering Laboratory, Toshiba Corporation, Yokohama, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ULSI Device Engineering Laboratory, Toshiba Corporation, Yokohama, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090578339","display_name":"Hiroshi Nakamura","orcid":"https://orcid.org/0009-0005-6505-1903","observed_orcids":["https://orcid.org/0009-0005-6505-1903"]},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"H. Nakamura","raw_affiliation_strings":["ULSI Device Engineering Laboratory, Toshiba Corporation, Yokohama, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ULSI Device Engineering Laboratory, Toshiba Corporation, Yokohama, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108839389","display_name":"K. Imamiya","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"K. Imamiya","raw_affiliation_strings":["ULSI Device Engineering Laboratory, Toshiba Corporation, Yokohama, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ULSI Device Engineering Laboratory, Toshiba Corporation, Yokohama, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111676830","display_name":"J. Miyamoto","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"J. Miyamoto","raw_affiliation_strings":["ULSI Device Engineering Laboratory, Toshiba Corporation, Yokohama, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ULSI Device Engineering Laboratory, Toshiba Corporation, Yokohama, Japan","institution_ids":["https://openalex.org/I1292669757"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1292669757"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.27612921,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"236","last_page":"237"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.35280001163482666,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.35280001163482666,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.28540000319480896,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.19529999792575836,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/nand-flash-memory","display_name":"NAND flash memory","score":0.9330000281333923},{"id":"https://openalex.org/keywords/threshold-voltage-distribution","display_name":"threshold voltage distribution","score":0.7889999747276306},{"id":"https://openalex.org/keywords/sense-amplifier","display_name":"sense amplifier","score":0.8679999709129333},{"id":"https://openalex.org/keywords/chip-size-reduction","display_name":"chip size reduction","score":0.6610000133514404}],"concepts":[{"id":"https://openalex.org/C117011727","wikidata":"https://www.wikidata.org/wiki/Q1278488","display_name":"Bit (key)","level":2,"score":0.8321176767349243},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.7898584604263306},{"id":"https://openalex.org/C27699510","wikidata":"https://www.wikidata.org/wiki/Q205908","display_name":"EEPROM","level":2,"score":0.7530725002288818},{"id":"https://openalex.org/C163980746","wikidata":"https://www.wikidata.org/wiki/Q378210","display_name":"EPROM","level":2,"score":0.6453126668930054},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6449412703514099},{"id":"https://openalex.org/C185177783","wikidata":"https://www.wikidata.org/wiki/Q3332814","display_name":"Megabit","level":2,"score":0.6299048662185669},{"id":"https://openalex.org/C32666082","wikidata":"https://www.wikidata.org/wiki/Q7450979","display_name":"Sense amplifier","level":3,"score":0.6208353638648987},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.5338445901870728},{"id":"https://openalex.org/C2776310492","wikidata":"https://www.wikidata.org/wiki/Q3271420","display_name":"12-bit","level":3,"score":0.49860501289367676},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4945947825908661},{"id":"https://openalex.org/C75695347","wikidata":"https://www.wikidata.org/wiki/Q225147","display_name":"32-bit","level":2,"score":0.4938128888607025},{"id":"https://openalex.org/C194986542","wikidata":"https://www.wikidata.org/wiki/Q229932","display_name":"4-bit","level":3,"score":0.47644951939582825},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.44154930114746094},{"id":"https://openalex.org/C7234692","wikidata":"https://www.wikidata.org/wiki/Q4116068","display_name":"NAND logic","level":4,"score":0.42888128757476807},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.39708030223846436},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.39006009697914124},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3878728151321411},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.36546245217323303},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.32775047421455383},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1731722354888916},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.10411012172698975},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.09899300336837769},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08055108785629272},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.07956498861312866}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsic.1998.688098","doi":"https://doi.org/10.1109/vlsic.1998.688098","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsic.1998.688098","pdf_url":null,"source":{"id":"https://openalex.org/S4393918263","display_name":"Symposium on VLSI Circuits","issn_l":"2166-9600","issn":["2166-9600"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":["jufo-1"],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320324367","display_name":"Volvo Research and Educational Foundations","ror":"https://ror.org/05n1rgb70"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W2071904073","https://openalex.org/W2162415926","https://openalex.org/W2397087819","https://openalex.org/W2789141633"],"related_works":["https://openalex.org/W2789050380","https://openalex.org/W2108812743","https://openalex.org/W1921542996","https://openalex.org/W2136221709","https://openalex.org/W1501895919","https://openalex.org/W2468261561","https://openalex.org/W3044696349","https://openalex.org/W2567632312","https://openalex.org/W2116241742","https://openalex.org/W2098551543"],"abstract_inverted_index":{"A":[0,25],"sophisticated":[1],"bit-by-bit":[2,27],"verifying":[3,28],"scheme,":[4],"which":[5],"is":[6,30],"able":[7],"to":[8],"realize":[9],"a":[10,33,38],"tight":[11],"programmed":[12],"threshold":[13],"voltage":[14],"distribution":[15],"of":[16,32,50],"0.8":[17],"V,":[18],"has":[19],"been":[20],"proposed":[21],"for":[22],"NAND":[23,54],"EEPROMs.":[24],"new":[26],"circuit":[29,41],"composed":[31],"conventional":[34],"sense":[35],"amplifier":[36],"and":[37],"dynamic":[39],"latch":[40],"with":[42],"only":[43],"three":[44],"transistors,":[45],"increasing":[46],"the":[47,51],"chip":[48],"size":[49],"64":[52],"Mbit":[53],"EEPROM":[55],"less":[56],"than":[57],"1%.":[58]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2026-10-06T10:28:23.643775","created_date":"2016-06-24T00:00:00"}
