{"id":"https://openalex.org/W2139085913","doi":"https://doi.org/10.1109/socdc.2008.4815649","title":"An effective parallel ALPG using instruction unrolling for high speed memory testing","display_name":"An effective parallel ALPG using instruction unrolling for high speed memory testing","publication_year":2008,"publication_date":"2008-11-01","ids":{"openalex":"https://openalex.org/W2139085913","doi":"https://doi.org/10.1109/socdc.2008.4815649","mag":"2139085913"},"language":"en","primary_location":{"id":"doi:10.1109/socdc.2008.4815649","doi":"https://doi.org/10.1109/socdc.2008.4815649","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socdc.2008.4815649","pdf_url":null,"source":{"id":"https://openalex.org/S4306420065","display_name":"International SoC Design Conference","issn_l":"2163-9612","issn":["2163-9612"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International SoC Design Conference","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5023290567","display_name":"Hyun-Jun Yoon","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Hyunjun Yoon","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","Dept of Electr. & Electron. Eng, Yonsei Univ., Seoul"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"Dept of Electr. & Electron. Eng, Yonsei Univ., Seoul","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102177625","display_name":"Myung-Hoon Yang","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Myung-Hoon Yang","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","Dept of Electr. & Electron. Eng, Yonsei Univ., Seoul"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"Dept of Electr. & Electron. Eng, Yonsei Univ., Seoul","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011001300","display_name":"Yongjoon Kim","orcid":"https://orcid.org/0000-0003-1531-9164","observed_orcids":["https://orcid.org/0000-0003-1531-9164"]},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Yongjoon Kim","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","Dept of Electr. & Electron. Eng, Yonsei Univ., Seoul"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"Dept of Electr. & Electron. Eng, Yonsei Univ., Seoul","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100724134","display_name":"Young\u2010Kyu Park","orcid":"https://orcid.org/0000-0003-4831-217X","observed_orcids":["https://orcid.org/0000-0003-4831-217X"]},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Youngkyu Park","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","Dept of Electr. & Electron. Eng, Yonsei Univ., Seoul"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"Dept of Electr. & Electron. Eng, Yonsei Univ., Seoul","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054644826","display_name":"Jaeseok Park","orcid":"https://orcid.org/0000-0002-8390-8166","observed_orcids":["https://orcid.org/0000-0002-8390-8166"]},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jaeseok Park","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","Dept of Electr. & Electron. Eng, Yonsei Univ., Seoul"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"Dept of Electr. & Electron. Eng, Yonsei Univ., Seoul","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068528309","display_name":"Sungho Kang","orcid":"https://orcid.org/0000-0002-7093-2095","observed_orcids":["https://orcid.org/0000-0002-7093-2095"]},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Sungho Kang","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","Dept of Electr. & Electron. Eng, Yonsei Univ., Seoul"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"Dept of Electr. & Electron. Eng, Yonsei Univ., Seoul","institution_ids":["https://openalex.org/I193775966"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I193775966"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.16278327,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"I","last_page":"370"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9556000232696533,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9556000232696533,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.017899999395012856,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12941","display_name":"Embedded Systems and FPGA Design","score":0.0052999998442828655,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-equipment","display_name":"automatic test equipment","score":0.7919999957084656},{"id":"https://openalex.org/keywords/memory-testing","display_name":"memory assessment","score":0.7900000214576721},{"id":"https://openalex.org/keywords/high-speed-testing","display_name":"high-speed testing","score":0.7049999833106995},{"id":"https://openalex.org/keywords/test-pattern-generation","display_name":"test pattern generation","score":0.6660000085830688}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8534314632415771},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.6130960583686829},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.5678471922874451},{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.5375502109527588},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5143531560897827},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4564824104309082},{"id":"https://openalex.org/C2780586882","wikidata":"https://www.wikidata.org/wiki/Q7520643","display_name":"Simple (philosophy)","level":2,"score":0.43704739212989807},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.4336169958114624},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4051315188407898},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3593176007270813},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.18924817442893982},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/socdc.2008.4815649","doi":"https://doi.org/10.1109/socdc.2008.4815649","is_oa":false,"landing_page_url":"https://doi.org/10.1109/socdc.2008.4815649","pdf_url":null,"source":{"id":"https://openalex.org/S4306420065","display_name":"International SoC Design Conference","issn_l":"2163-9612","issn":["2163-9612"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 International SoC Design Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1595368737","https://openalex.org/W1676973727","https://openalex.org/W1819226324","https://openalex.org/W1849928240","https://openalex.org/W2110446288","https://openalex.org/W2160042770","https://openalex.org/W2162567463","https://openalex.org/W2553126414","https://openalex.org/W3014325818"],"related_works":["https://openalex.org/W2400165543","https://openalex.org/W4391640275","https://openalex.org/W4404056580","https://openalex.org/W4404848570","https://openalex.org/W7137848304","https://openalex.org/W1676973727","https://openalex.org/W4387486061","https://openalex.org/W2160042770","https://openalex.org/W4360604915","https://openalex.org/W2115046209"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"the":[3,21,28,34,48,51,56,71,82,92,96],"design":[4],"and":[5,86],"implementation":[6],"of":[7,15,50,73,95],"a":[8],"new":[9],"parallel":[10],"Algorithmic":[11],"Pattern":[12,75],"Generator":[13],"(ALPG)":[14],"Automatic":[16],"Test":[17],"Equipment":[18],"(ATE)":[19],"for":[20],"high":[22,63,66,89,93],"speed":[23,90],"memory":[24,42],"testing.":[25],"We":[26],"implemented":[27,45],"Instruction":[29],"Analyzer":[30],"(IA)":[31],"that":[32],"unrolls":[33],"instructions":[35],"using":[36],"simple":[37],"instructions.":[38],"And,":[39],"unrolled":[40],"instruction":[41],"is":[43],"also":[44,69],"to":[46,58],"reduce":[47],"delay":[49],"IA.":[52],"These":[53],"implementations":[54],"allow":[55],"ALPG":[57,72,83],"operate":[59],"flexible":[60],"algorithms":[61],"at":[62,88],"speed.":[64],"For":[65],"speed,":[67],"we":[68],"designed":[70],"multiple":[74],"Generators":[76],"(PG)":[77],"with":[78,91],"phase-shifting":[79],"clocks.":[80],"Therefore,":[81],"has":[84],"expandability":[85],"operates":[87],"flexibility":[94],"algorithms.":[97]},"counts_by_year":[{"year":2026,"cited_by_count":3},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":2}],"updated_date":"2026-11-07T11:25:07.637180","created_date":"2016-06-24T00:00:00"}