{"id":"https://openalex.org/W2138874875","doi":null,"title":"A versatile generator of instruction set simulators and disassemblers","display_name":"A versatile generator of instruction set simulators and disassemblers","publication_year":2009,"publication_date":"2009-07-13","ids":{"openalex":"https://openalex.org/W2138874875","mag":"2138874875"},"language":"en","primary_location":{"id":"mag:2138874875","doi":null,"is_oa":false,"landing_page_url":"https://ieeexplore.ieee.org/document/5224142/","pdf_url":null,"source":{"id":"https://openalex.org/S4306420194","display_name":"International Symposium on Performance Evaluation of Computer and Telecommunication Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":"International Symposium on Performance Evaluation of Computer and Telecommunication Systems","raw_type":null},"parent_works":[],"lineage":["https://openalex.org/W2138874875"],"child_works_count":0,"type":"conference-paper","is_traditional":true,"indexed_in":[],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054962476","display_name":"Tahiry Ratsiambahotra","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I134560555","display_name":"Universit\u00e9 Toulouse III - Paul Sabatier","ror":"https://ror.org/02v6kpv12","country_code":"FR","type":"education","lineage":["https://openalex.org/I134560555","https://openalex.org/I4405258862"]},{"id":"https://openalex.org/I4210119061","display_name":"Institut de Recherche en Informatique de Toulouse","ror":"https://ror.org/01rx4qw44","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I205747304","https://openalex.org/I4210119061","https://openalex.org/I4210152422","https://openalex.org/I4405258862","https://openalex.org/I4405259414"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Tahiry Ratsiambahotra","raw_affiliation_strings":["IRIT - Universit\u00e9 Paul Sabatier de Toulouse, Hipeac European Network of Excellence, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IRIT - Universit\u00e9 Paul Sabatier de Toulouse, Hipeac European Network of Excellence, France","institution_ids":["https://openalex.org/I134560555","https://openalex.org/I4210119061"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006018472","display_name":"Hugues Cass\u00e9","orcid":"https://orcid.org/0000-0002-9298-5235","observed_orcids":["https://orcid.org/0000-0002-9298-5235"]},"institutions":[{"id":"https://openalex.org/I134560555","display_name":"Universit\u00e9 Toulouse III - Paul Sabatier","ror":"https://ror.org/02v6kpv12","country_code":"FR","type":"education","lineage":["https://openalex.org/I134560555","https://openalex.org/I4405258862"]},{"id":"https://openalex.org/I4210119061","display_name":"Institut de Recherche en Informatique de Toulouse","ror":"https://ror.org/01rx4qw44","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I205747304","https://openalex.org/I4210119061","https://openalex.org/I4210152422","https://openalex.org/I4405258862","https://openalex.org/I4405259414"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Hugues Cass\u00e9","raw_affiliation_strings":["IRIT - Universit\u00e9 Paul Sabatier de Toulouse, Hipeac European Network of Excellence, France"],"raw_orcid":"https://orcid.org/0000-0002-9298-5235","affiliations":[{"raw_affiliation_string":"IRIT - Universit\u00e9 Paul Sabatier de Toulouse, Hipeac European Network of Excellence, France","institution_ids":["https://openalex.org/I134560555","https://openalex.org/I4210119061"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084795370","display_name":"Pascal Sainrat","orcid":"https://orcid.org/0000-0003-1039-2290","observed_orcids":["https://orcid.org/0000-0003-1039-2290"]},"institutions":[{"id":"https://openalex.org/I134560555","display_name":"Universit\u00e9 Toulouse III - Paul Sabatier","ror":"https://ror.org/02v6kpv12","country_code":"FR","type":"education","lineage":["https://openalex.org/I134560555","https://openalex.org/I4405258862"]},{"id":"https://openalex.org/I4210119061","display_name":"Institut de Recherche en Informatique de Toulouse","ror":"https://ror.org/01rx4qw44","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I205747304","https://openalex.org/I4210119061","https://openalex.org/I4210152422","https://openalex.org/I4405258862","https://openalex.org/I4405259414"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Pascal Sainrat","raw_affiliation_strings":["IRIT - Universit\u00e9 Paul Sabatier de Toulouse, Hipeac European Network of Excellence, France"],"raw_orcid":"https://orcid.org/0000-0003-1039-2290","affiliations":[{"raw_affiliation_string":"IRIT - Universit\u00e9 Paul Sabatier de Toulouse, Hipeac European Network of Excellence, France","institution_ids":["https://openalex.org/I134560555","https://openalex.org/I4210119061"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.0799,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.75710792,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":88,"max":95},"biblio":{"volume":"41","issue":null,"first_page":"65","last_page":"72"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.8955000042915344,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.8955000042915344,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.09099999815225601,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.00139999995008111,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/instruction-set-simulator","display_name":"instruction set simulator","score":0.8420000076293945},{"id":"https://openalex.org/keywords/disassembler","display_name":"disassembler","score":0.8669999837875366},{"id":"https://openalex.org/keywords/cycle-accurate-simulation","display_name":"cycle-accurate simulation","score":0.8700000047683716},{"id":"https://openalex.org/keywords/very-long-instruction-word","display_name":"VLIW","score":0.6370000243186951},{"id":"https://openalex.org/keywords/cisc","display_name":"CISC","score":0.8240000009536743},{"id":"https://openalex.org/keywords/risc","display_name":"RISC","score":0.9160000085830688},{"id":"https://openalex.org/keywords/x86","display_name":"x86","score":0.753000020980835},{"id":"https://openalex.org/keywords/arm","display_name":"arms","score":0.5070000290870667},{"id":"https://openalex.org/keywords/sharc","display_name":"SHARC","score":0.7919999957084656},{"id":"https://openalex.org/keywords/ppc","display_name":"PPC","score":0.6620000004768372},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"design space exploration","score":0.7170000076293945},{"id":"https://openalex.org/keywords/functional-testing","display_name":"functional testing","score":0.4790000021457672}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8499624729156494},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.7266970872879028},{"id":"https://openalex.org/C170595534","wikidata":"https://www.wikidata.org/wiki/Q249743","display_name":"Very long instruction word","level":2,"score":0.7235478162765503},{"id":"https://openalex.org/C170723468","wikidata":"https://www.wikidata.org/wiki/Q182933","display_name":"x86","level":3,"score":0.6098425388336182},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6071114540100098},{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.5544268488883972},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.5464367866516113},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5425906181335449},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.4230427145957947},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4223771393299103},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.3905768394470215},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.24125561118125916},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.18391147255897522},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"mag:2138874875","doi":null,"is_oa":false,"landing_page_url":"https://ieeexplore.ieee.org/document/5224142/","pdf_url":null,"source":{"id":"https://openalex.org/S4306420194","display_name":"International Symposium on Performance Evaluation of Computer and Telecommunication Systems","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":"International Symposium on Performance Evaluation of Computer and Telecommunication Systems","raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2091788277","https://openalex.org/W2102278953","https://openalex.org/W2107098293","https://openalex.org/W2112537029","https://openalex.org/W2130263644","https://openalex.org/W2131493012","https://openalex.org/W2138362897","https://openalex.org/W2141711229","https://openalex.org/W2591741338"],"related_works":["https://openalex.org/W2131493012","https://openalex.org/W4243690139","https://openalex.org/W7095686799","https://openalex.org/W1606763973","https://openalex.org/W1553912323","https://openalex.org/W2007071800","https://openalex.org/W7099416073","https://openalex.org/W813184419","https://openalex.org/W2168519412","https://openalex.org/W2102043677"],"abstract_inverted_index":{"Instruction-set":[0],"simulators":[1,18,109],"(ISS)":[2],"are":[3,19,65],"more":[4,6],"and":[5,12,59,81,90,101,110],"used":[7,102],"in":[8,67],"design":[9],"space":[10],"exploration":[11],"functional":[13,24],"software":[14],"testing.":[15],"Furthermore,":[16],"cycle-accurate":[17],"often":[20,39],"made":[21,114],"of":[22,55],"a":[23,27,68],"coupled":[25],"to":[26,51,60,75,93],"timing":[28],"simulator.":[29],"Research":[30],"about":[31],"ISS":[32],"generators":[33],"is":[34,91],"not":[35],"new":[36],"but":[37],"most":[38],"addresses":[40],"only":[41],"simple":[42],"instruction":[43],"sets":[44],"(i.e.":[45],"RISC).":[46],"This":[47],"paper":[48],"describes":[49],"techniques":[50],"ease":[52],"the":[53,116],"description":[54],"complex":[56],"Instruction-Set":[57],"Architectures":[58],"increase":[61],"simulation":[62],"speed.":[63],"They":[64],"integrated":[66],"tool":[69],"which":[70],"generates":[71],"libraries":[72],"containing":[73],"functions":[74],"disassemble":[76],"(useful":[77],"for":[78],"testing),":[79],"decode":[80],"simulate":[82],"many":[83],"different":[84],"architectures":[85],"like":[86],"RISC,":[87],"CISC,":[88],"VLIW":[89],"able":[92],"deal":[94],"with":[95],"variable-length":[96],"instructions.":[97],"We":[98],"successfully":[99],"generated":[100],"ARM/thumb,":[103],"HCS":[104],"12X,":[105],"Tricore,":[106],"Sharc,":[107],"PPC":[108],"experiments":[111],"have":[112],"been":[113],"on":[115],"x86":[117],"architecture.":[118]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-11-14T11:04:58.165337","created_date":"2016-06-24T00:00:00"}
