{"id":"https://openalex.org/W2129459494","doi":"https://doi.org/10.1109/4.387066","title":"Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications","display_name":"Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications","publication_year":1995,"publication_date":"1995-06-01","ids":{"openalex":"https://openalex.org/W2129459494","doi":"https://doi.org/10.1109/4.387066","mag":"2129459494"},"language":"en","primary_location":{"id":"doi:10.1109/4.387066","doi":"https://doi.org/10.1109/4.387066","is_oa":false,"landing_page_url":"https://doi.org/10.1109/4.387066","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","dongbi-a","jufo-3","norway-2","poland-140","russia-white-list-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"},"volume":null,"type":"article","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031412686","display_name":"Tsukasa Kimura","orcid":"https://orcid.org/0000-0002-9618-1701","observed_orcids":["https://orcid.org/0000-0002-9618-1701"]},"institutions":[{"id":"https://openalex.org/I118347220","display_name":"NEC (Japan)","ror":"https://ror.org/04jndar25","country_code":"JP","type":"company","lineage":["https://openalex.org/I118347220"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"T. Kimura","raw_affiliation_strings":["System ULSI Research Laboratory, Microelectronics Research Laboratories, NEC Corporation Limited, Sagamihara, Kanagawa, Japan","Syst. ULSI Res. Lab., NEC Corp., Sagamihara, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"System ULSI Research Laboratory, Microelectronics Research Laboratories, NEC Corporation Limited, Sagamihara, Kanagawa, Japan","institution_ids":["https://openalex.org/I118347220"]},{"raw_affiliation_string":"Syst. ULSI Res. Lab., NEC Corp., Sagamihara, Japan","institution_ids":["https://openalex.org/I118347220"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000876079","display_name":"Kazuyuki Nakamura","orcid":"https://orcid.org/0000-0002-9128-5229","observed_orcids":["https://orcid.org/0000-0002-9128-5229"]},"institutions":[{"id":"https://openalex.org/I118347220","display_name":"NEC (Japan)","ror":"https://ror.org/04jndar25","country_code":"JP","type":"company","lineage":["https://openalex.org/I118347220"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"K. Nakamura","raw_affiliation_strings":["System ULSI Research Laboratory, Microelectronics Research Laboratories, NEC Corporation Limited, Sagamihara, Kanagawa, Japan","Syst. ULSI Res. Lab., NEC Corp., Sagamihara, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"System ULSI Research Laboratory, Microelectronics Research Laboratories, NEC Corporation Limited, Sagamihara, Kanagawa, Japan","institution_ids":["https://openalex.org/I118347220"]},{"raw_affiliation_string":"Syst. ULSI Res. Lab., NEC Corp., Sagamihara, Japan","institution_ids":["https://openalex.org/I118347220"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027023457","display_name":"Yoshiharu Aimoto","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I118347220","display_name":"NEC (Japan)","ror":"https://ror.org/04jndar25","country_code":"JP","type":"company","lineage":["https://openalex.org/I118347220"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Y. Aimoto","raw_affiliation_strings":["System ULSI Research Laboratory, Microelectronics Research Laboratories, NEC Corporation Limited, Sagamihara, Kanagawa, Japan","Syst. ULSI Res. Lab., NEC Corp., Sagamihara, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"System ULSI Research Laboratory, Microelectronics Research Laboratories, NEC Corporation Limited, Sagamihara, Kanagawa, Japan","institution_ids":["https://openalex.org/I118347220"]},{"raw_affiliation_string":"Syst. ULSI Res. Lab., NEC Corp., Sagamihara, Japan","institution_ids":["https://openalex.org/I118347220"]}]},{"author_position":"middle","author":{"id":null,"display_name":"T. Manabe","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I118347220","display_name":"NEC (Japan)","ror":"https://ror.org/04jndar25","country_code":"JP","type":"company","lineage":["https://openalex.org/I118347220"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"T. Manabe","raw_affiliation_strings":["System ULSI Research Laboratory, Microelectronics Research Laboratories, NEC Corporation Limited, Sagamihara, Kanagawa, Japan","Syst. ULSI Res. Lab., NEC Corp., Sagamihara, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"System ULSI Research Laboratory, Microelectronics Research Laboratories, NEC Corporation Limited, Sagamihara, Kanagawa, Japan","institution_ids":["https://openalex.org/I118347220"]},{"raw_affiliation_string":"Syst. ULSI Res. Lab., NEC Corp., Sagamihara, Japan","institution_ids":["https://openalex.org/I118347220"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112125616","display_name":"N. Yamashita","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I118347220","display_name":"NEC (Japan)","ror":"https://ror.org/04jndar25","country_code":"JP","type":"company","lineage":["https://openalex.org/I118347220"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"N. Yamashita","raw_affiliation_strings":["System ULSI Research Laboratory, Microelectronics Research Laboratories, NEC Corporation Limited, Sagamihara, Kanagawa, Japan","Syst. ULSI Res. Lab., NEC Corp., Sagamihara, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"System ULSI Research Laboratory, Microelectronics Research Laboratories, NEC Corporation Limited, Sagamihara, Kanagawa, Japan","institution_ids":["https://openalex.org/I118347220"]},{"raw_affiliation_string":"Syst. ULSI Res. Lab., NEC Corp., Sagamihara, Japan","institution_ids":["https://openalex.org/I118347220"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061303565","display_name":"Yasuhiko Fujita","orcid":"https://orcid.org/0000-0003-1302-1436","observed_orcids":["https://orcid.org/0000-0003-1302-1436"]},"institutions":[{"id":"https://openalex.org/I118347220","display_name":"NEC (Japan)","ror":"https://ror.org/04jndar25","country_code":"JP","type":"company","lineage":["https://openalex.org/I118347220"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Y. Fujita","raw_affiliation_strings":["System ULSI Research Laboratory, Microelectronics Research Laboratories, NEC Corporation Limited, Sagamihara, Kanagawa, Japan","Syst. ULSI Res. Lab., NEC Corp., Sagamihara, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"System ULSI Research Laboratory, Microelectronics Research Laboratories, NEC Corporation Limited, Sagamihara, Kanagawa, Japan","institution_ids":["https://openalex.org/I118347220"]},{"raw_affiliation_string":"Syst. ULSI Res. Lab., NEC Corp., Sagamihara, Japan","institution_ids":["https://openalex.org/I118347220"]}]},{"author_position":"middle","author":{"id":null,"display_name":"S. Okazaki","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I118347220","display_name":"NEC (Japan)","ror":"https://ror.org/04jndar25","country_code":"JP","type":"company","lineage":["https://openalex.org/I118347220"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"S. Okazaki","raw_affiliation_strings":["System ULSI Research Laboratory, Microelectronics Research Laboratories, NEC Corporation Limited, Sagamihara, Kanagawa, Japan","Syst. ULSI Res. Lab., NEC Corp., Sagamihara, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"System ULSI Research Laboratory, Microelectronics Research Laboratories, NEC Corporation Limited, Sagamihara, Kanagawa, Japan","institution_ids":["https://openalex.org/I118347220"]},{"raw_affiliation_string":"Syst. ULSI Res. Lab., NEC Corp., Sagamihara, Japan","institution_ids":["https://openalex.org/I118347220"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5077058014","display_name":"M. Yamashina","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I118347220","display_name":"NEC (Japan)","ror":"https://ror.org/04jndar25","country_code":"JP","type":"company","lineage":["https://openalex.org/I118347220"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"M. Yamashina","raw_affiliation_strings":["System ULSI Research Laboratory, Microelectronics Research Laboratories, NEC Corporation Limited, Sagamihara, Kanagawa, Japan","Syst. ULSI Res. Lab., NEC Corp., Sagamihara, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"System ULSI Research Laboratory, Microelectronics Research Laboratories, NEC Corporation Limited, Sagamihara, Kanagawa, Japan","institution_ids":["https://openalex.org/I118347220"]},{"raw_affiliation_string":"Syst. ULSI Res. Lab., NEC Corp., Sagamihara, Japan","institution_ids":["https://openalex.org/I118347220"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I118347220"],"apc_list":{"value":2645,"currency":"USD","value_usd":2645},"apc_paid":null,"fwci":0.4635,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.58422058,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"30","issue":"6","first_page":"637","last_page":"643"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9702000021934509,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9702000021934509,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.011800000444054604,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.00430000014603138,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/sram","display_name":"SRAM","score":0.9089999794960022},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"memory bandwidth","score":0.8080000281333923},{"id":"https://openalex.org/keywords/low-power-consumption","display_name":"low power consumption","score":0.656000018119812},{"id":"https://openalex.org/keywords/dynamic-power-control","display_name":"dynamic power control","score":0.9290000200271606},{"id":"https://openalex.org/keywords/memory-access-time","display_name":"memory access time","score":0.8029999732971191},{"id":"https://openalex.org/keywords/processing-elements","display_name":"processing elements","score":0.42399999499320984},{"id":"https://openalex.org/keywords/lsi-design","display_name":"LSI design","score":0.6430000066757202}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7772096991539001},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.633963942527771},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.568979799747467},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5592547655105591},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.5481446981430054},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5416934490203857},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.476868212223053},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.470826655626297},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.46819743514060974},{"id":"https://openalex.org/C194080101","wikidata":"https://www.wikidata.org/wiki/Q46306","display_name":"Access time","level":2,"score":0.4439469575881958},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.4411279559135437},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4359324872493744},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.4201873540878296},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.31636863946914673},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.28081220388412476},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1277044415473938},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0879371166229248},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/4.387066","doi":"https://doi.org/10.1109/4.387066","is_oa":false,"landing_page_url":"https://doi.org/10.1109/4.387066","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","dongbi-a","jufo-3","norway-2","poland-140","russia-white-list-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Journal of Solid-State Circuits","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W407317322","https://openalex.org/W1994593330","https://openalex.org/W2003459643","https://openalex.org/W2110874443","https://openalex.org/W2154457027","https://openalex.org/W2161719036"],"related_works":["https://openalex.org/W4244288358","https://openalex.org/W2106418199","https://openalex.org/W4286571776","https://openalex.org/W2024432593","https://openalex.org/W1994593330","https://openalex.org/W3010128671","https://openalex.org/W2153220986","https://openalex.org/W7116879602","https://openalex.org/W1556661488","https://openalex.org/W7098404064"],"abstract_inverted_index":{"We":[0,56],"have":[1],"fabricated":[2],"a":[3,14,28,99],"high":[4,15],"yield":[5],"integrated":[6,120],"memory":[7,16,45,62,89],"array":[8],"processor":[9,35],"(IMAP)":[10],"LSI,":[11],"which":[12,26,86],"features":[13],"bandwidth":[17],"(1.28-GB/s)":[18],"and":[19,25,33,43],"low":[20],"power":[21,83,90,97],"consumption":[22,91],"(4-W":[23],"max.)":[24],"contains":[27],"2-Mb":[29],"SRAM":[30],"with":[31,106],"1.28-I/O's":[32],"64":[34],"elements":[36],"(PE's)":[37],"in":[38,101],"one":[39],"chip.":[40],"A":[41],"high-bandwidth":[42],"low-power":[44],"circuit":[46],"design":[47,113],"is":[48,68],"the":[49,54,88],"key":[50],"technology":[51],"to":[52,70,93],"realize":[53],"IMAP-LSI.":[55],"adopted":[57],"following":[58],"new":[59],"designs":[60],"for":[61,117],"circuit.":[63],"(1)":[64],"Memory":[65],"access":[66],"time":[67,78],"designed":[69],"be":[71],"twice":[72],"as":[73,75],"fast":[74],"PE":[76],"execution":[77],"(2)":[79],"Employment":[80],"of":[81,95],"dynamic":[82],"control":[84],"mode,":[85],"reduces":[87],"down":[92],"30%":[94],"maximum":[96],"without":[98],"loss":[100],"access-speed":[102],"(3)":[103],"Simplified":[104],"synchronization":[105],"PE's":[107],"(4)":[108],"4-way":[109],"block":[110],"redundancy.":[111],"These":[112],"techniques":[114],"are":[115],"suitable":[116],"future":[118],"system":[119],"ULSI's.>":[121]},"counts_by_year":[],"updated_date":"2026-09-29T14:09:16.559479","created_date":"2016-06-24T00:00:00"}
