{"id":"https://openalex.org/W2129069730","doi":"https://doi.org/10.1109/ismvl.1999.779714","title":"Down literal circuit with neuron-MOS transistors and its applications","display_name":"Down literal circuit with neuron-MOS transistors and its applications","publication_year":2003,"publication_date":"2003-01-20","ids":{"openalex":"https://openalex.org/W2129069730","doi":"https://doi.org/10.1109/ismvl.1999.779714","mag":"2129069730"},"language":"en","primary_location":{"id":"doi:10.1109/ismvl.1999.779714","doi":"https://doi.org/10.1109/ismvl.1999.779714","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ismvl.1999.779714","pdf_url":null,"source":{"id":"https://openalex.org/S4210220027","display_name":"IEEE International Symposium on Multiple-Valued Logic (ISMVL)","issn_l":"0195-623X","issn":["0195-623X","2378-2226"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","jufo-1","norway-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 1999 29th IEEE International Symposium on Multiple-Valued Logic (Cat. No.99CB36329)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103252123","display_name":"Jing Shuang Shen","orcid":"https://orcid.org/0000-0003-1231-6590","observed_orcids":["https://orcid.org/0000-0003-1231-6590"]},"institutions":[{"id":"https://openalex.org/I118574687","display_name":"University of Miyazaki","ror":"https://ror.org/0447kww10","country_code":"JP","type":"education","lineage":["https://openalex.org/I118574687"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Jing Shen","raw_affiliation_strings":["Miyazaki University, Miyazaki, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Miyazaki University, Miyazaki, Japan","institution_ids":["https://openalex.org/I118574687"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101777998","display_name":"Koichi Tanno","orcid":"https://orcid.org/0000-0003-3548-5178","observed_orcids":["https://orcid.org/0000-0003-3548-5178"]},"institutions":[{"id":"https://openalex.org/I118574687","display_name":"University of Miyazaki","ror":"https://ror.org/0447kww10","country_code":"JP","type":"education","lineage":["https://openalex.org/I118574687"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"K. Tanno","raw_affiliation_strings":["Miyazaki University, Miyazaki, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Miyazaki University, Miyazaki, Japan","institution_ids":["https://openalex.org/I118574687"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072469129","display_name":"Okihiko Ishizuka","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I118574687","display_name":"University of Miyazaki","ror":"https://ror.org/0447kww10","country_code":"JP","type":"education","lineage":["https://openalex.org/I118574687"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"O. Ishizuka","raw_affiliation_strings":["Miyazaki University, Miyazaki, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Miyazaki University, Miyazaki, Japan","institution_ids":["https://openalex.org/I118574687"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I118574687"],"apc_list":null,"apc_paid":null,"fwci":3.1395,"has_fulltext":false,"cited_by_count":20,"citation_normalized_percentile":{"value":0.92272993,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":88,"max":97},"biblio":{"volume":"j71 d","issue":null,"first_page":"180","last_page":"185"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.49900001287460327,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.49900001287460327,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.2583000063896179,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.093299999833107,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos-implementation","display_name":"CMOS implementation","score":0.5580000281333923},{"id":"https://openalex.org/keywords/noise-margin","display_name":"noise margin","score":0.6460000276565552},{"id":"https://openalex.org/keywords/threshold-voltage-mismatch","display_name":"threshold voltage mismatch","score":0.7839999794960022},{"id":"https://openalex.org/keywords/t-gate","display_name":"T-gate","score":0.6470000147819519}],"concepts":[{"id":"https://openalex.org/C2780882242","wikidata":"https://www.wikidata.org/wiki/Q14235582","display_name":"Literal (mathematical logic)","level":2,"score":0.8788349628448486},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6659712791442871},{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.6583936810493469},{"id":"https://openalex.org/C195370968","wikidata":"https://www.wikidata.org/wiki/Q1754002","display_name":"Threshold voltage","level":4,"score":0.6112686395645142},{"id":"https://openalex.org/C179499742","wikidata":"https://www.wikidata.org/wiki/Q1324892","display_name":"Noise margin","level":4,"score":0.576598048210144},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5308120250701904},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5116291642189026},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.5004117488861084},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.492815762758255},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.47971075773239136},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4712434411048889},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4350378215312958},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2723599076271057},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.13413670659065247}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ismvl.1999.779714","doi":"https://doi.org/10.1109/ismvl.1999.779714","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ismvl.1999.779714","pdf_url":null,"source":{"id":"https://openalex.org/S4210220027","display_name":"IEEE International Symposium on Multiple-Valued Logic (ISMVL)","issn_l":"0195-623X","issn":["0195-623X","2378-2226"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","jufo-1","norway-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 1999 29th IEEE International Symposium on Multiple-Valued Logic (Cat. No.99CB36329)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1530161807","https://openalex.org/W1905953118","https://openalex.org/W2006097283","https://openalex.org/W2160142098","https://openalex.org/W6631745131"],"related_works":["https://openalex.org/W2341949915","https://openalex.org/W2151483146","https://openalex.org/W2119305096","https://openalex.org/W1998847131","https://openalex.org/W2411104301","https://openalex.org/W2545117335","https://openalex.org/W1530161807","https://openalex.org/W2084656699","https://openalex.org/W2073567346","https://openalex.org/W2044263958"],"abstract_inverted_index":{"A":[0],"voltage-mode":[1],"neuron-MOS(/spl":[2],"nu/MOS)":[3],"down":[4,11,92],"literal":[5,12,93,95],"circuit":[6,22,79],"which":[7],"realizes":[8],"an":[9],"arbitrary":[10],"function":[13],"is":[14,85],"proposed.":[15],"It":[16,42],"provides":[17],"the":[18,21,33,39,78,89,104],"benefit":[19],"that":[20],"can":[23],"be":[24],"easily":[25],"fabricated":[26],"by":[27,48,71,81],"standard":[28],"CMOS":[29,117],"process,":[30],"instead":[31],"of":[32,50,66,77,103],"multi-level":[34],"ion":[35],"implantation":[36],"applied":[37],"in":[38],"conventional":[40],"circuit.":[41],"has":[43],"a":[44],"variable":[45],"threshold":[46,74],"voltage":[47,75],"way":[49],"controlling":[51],"only":[52],"two":[53],"bias":[54],"voltages.":[55],"Its":[56],"noise":[57],"margin":[58],"and":[59,96],"switching":[60],"sensitivity":[61],"are":[62,99,107],"greater":[63],"than":[64],"those":[65],"variable-threshold":[67],"C-VMOS":[68],"inverter":[69],"presented":[70],"Shibata.":[72],"The":[73],"errors":[76],"caused":[80],"device":[82,118],"parameters":[83],"mismatch":[84],"also":[86,100],"analysed.":[87],"Using":[88],"/spl":[90,115],"nu/MOS":[91],"circuits,":[94],"T-gate":[97],"circuits":[98,106],"presented.":[101],"Performances":[102],"proposed":[105],"evaluated":[108],"using":[109],"HSPICE":[110],"simulations":[111],"with":[112],"MOSIS":[113],"2.0":[114],"mu/m":[116],"parameters.":[119]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":1}],"updated_date":"2026-11-04T10:54:05.112534","created_date":"2016-06-24T00:00:00"}