{"id":"https://openalex.org/W2128761959","doi":"https://doi.org/10.1109/fpl.2005.1515750","title":"On-chip communication topology synthesis for shared multi-bus based architecture","display_name":"On-chip communication topology synthesis for shared multi-bus based architecture","publication_year":2005,"publication_date":"2005-10-12","ids":{"openalex":"https://openalex.org/W2128761959","doi":"https://doi.org/10.1109/fpl.2005.1515750","mag":"2128761959"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2005.1515750","doi":"https://doi.org/10.1109/fpl.2005.1515750","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2005.1515750","pdf_url":null,"source":{"id":"https://openalex.org/S7407085929","display_name":"International Conference on Field Programmable Logic and Applications (FPL)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Conference on Field Programmable Logic and Applications, 2005.","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000000560","display_name":"Sujan Pandey","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technische Universit\u00e4t Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"S. Pandey","raw_affiliation_strings":["Institute of Microelectronics Systems, Darmstadt University of Technology, Germany","Inst. of Microelectron. Systems, Darmstadt Univ. of Technol., Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics Systems, Darmstadt University of Technology, Germany","institution_ids":["https://openalex.org/I31512782"]},{"raw_affiliation_string":"Inst. of Microelectron. Systems, Darmstadt Univ. of Technol., Germany","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002162776","display_name":"Manfred Glesner","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technische Universit\u00e4t Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"M. Glesner","raw_affiliation_strings":["Institute of Microelectronics Systems, Darmstadt University of Technology, Germany","Inst. of Microelectron. Systems, Darmstadt Univ. of Technol., Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics Systems, Darmstadt University of Technology, Germany","institution_ids":["https://openalex.org/I31512782"]},{"raw_affiliation_string":"Inst. of Microelectron. Systems, Darmstadt Univ. of Technol., Germany","institution_ids":["https://openalex.org/I31512782"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021712397","display_name":"Max M\u00fchlh\u00e4user","orcid":"https://orcid.org/0000-0003-4713-5327","observed_orcids":["https://orcid.org/0000-0003-4713-5327"]},"institutions":[{"id":"https://openalex.org/I31512782","display_name":"Technische Universit\u00e4t Darmstadt","ror":"https://ror.org/05n911h24","country_code":"DE","type":"education","lineage":["https://openalex.org/I31512782"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"M. Muhlhauser","raw_affiliation_strings":["Telecooperation Group, Darmstadt University of Technology, Germany","Technische Universit\u00e4t Darmstadt"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Telecooperation Group, Darmstadt University of Technology, Germany","institution_ids":["https://openalex.org/I31512782"]},{"raw_affiliation_string":"Technische Universit\u00e4t Darmstadt","institution_ids":["https://openalex.org/I31512782"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I31512782"],"apc_list":null,"apc_paid":null,"fwci":1.2426,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.80223947,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":88,"max":93},"biblio":{"volume":"cad 5","issue":null,"first_page":"374","last_page":"379"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.861299991607666,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.861299991607666,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.09640000015497208,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.04039999842643738,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/integer-linear-programming","display_name":"integer linear programming","score":0.8059999942779541},{"id":"https://openalex.org/keywords/system-partitioning","display_name":"system partitioning","score":0.6710000038146973},{"id":"https://openalex.org/keywords/system-on-chip","display_name":"system-on-chip","score":0.6460000276565552},{"id":"https://openalex.org/keywords/ubiquitous-computing","display_name":"ubiquitous computing","score":0.9789999723434448}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7771963477134705},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6499783992767334},{"id":"https://openalex.org/C54609922","wikidata":"https://www.wikidata.org/wiki/Q748329","display_name":"Bus network","level":4,"score":0.593781590461731},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.562623143196106},{"id":"https://openalex.org/C136321198","wikidata":"https://www.wikidata.org/wiki/Q2377054","display_name":"System bus","level":2,"score":0.5577248334884644},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.5393012166023254},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.532723069190979},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5211898684501648},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.49578818678855896},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4887223243713379},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.48212599754333496},{"id":"https://openalex.org/C56086750","wikidata":"https://www.wikidata.org/wiki/Q6042592","display_name":"Integer programming","level":2,"score":0.4631950259208679},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.4570808708667755},{"id":"https://openalex.org/C97137487","wikidata":"https://www.wikidata.org/wiki/Q729138","display_name":"Integer (computer science)","level":2,"score":0.4522843062877655},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42292076349258423},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3722500205039978},{"id":"https://openalex.org/C203315745","wikidata":"https://www.wikidata.org/wiki/Q2235486","display_name":"Control bus","level":3,"score":0.3543800711631775},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3417856693267822},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.27927765250205994},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.2484985589981079},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.17115342617034912},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10550710558891296},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07864728569984436},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07063579559326172},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/fpl.2005.1515750","doi":"https://doi.org/10.1109/fpl.2005.1515750","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2005.1515750","pdf_url":null,"source":{"id":"https://openalex.org/S7407085929","display_name":"International Conference on Field Programmable Logic and Applications (FPL)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Conference on Field Programmable Logic and Applications, 2005.","raw_type":"proceedings-article"},{"id":"pmh:oai:tubiblio.ulb.tu-darmstadt.de:27151","doi":null,"is_oa":false,"landing_page_url":"http://tubiblio.ulb.tu-darmstadt.de/27151/","pdf_url":null,"source":{"id":"https://openalex.org/S4377196390","display_name":"TUbilio (Technical University of Darmstadt)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I31512782","host_organization_name":"Technische Universit\u00e4t Darmstadt","host_organization_lineage":["https://openalex.org/I31512782"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Konferenzver\u00f6ffentlichung"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5378999710083008,"display_name":"Industry, innovation and infrastructure"}],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1045903774","https://openalex.org/W2032570700","https://openalex.org/W2053415041","https://openalex.org/W2063747323","https://openalex.org/W2137185684","https://openalex.org/W2158422562","https://openalex.org/W2159247054","https://openalex.org/W2161452437","https://openalex.org/W2167378481","https://openalex.org/W2493581502","https://openalex.org/W4249840435","https://openalex.org/W4285719527","https://openalex.org/W6627059904"],"related_works":["https://openalex.org/W3144005314","https://openalex.org/W2533829329","https://openalex.org/W2489019757","https://openalex.org/W2161823020","https://openalex.org/W2134879629","https://openalex.org/W2067205866","https://openalex.org/W2300672401","https://openalex.org/W2109672397","https://openalex.org/W2147708520","https://openalex.org/W7099866241"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,11,36,64,142,151],"method":[4],"of":[5,35,41,60,66,76,78,83,90,114,121,137],"on-chip":[6,51,144],"commaunication":[7],"topology":[8,107],"synthesis":[9,20,108],"for":[10,18,150],"shared":[12,145],"multi-bus":[13],"based":[14,147],"architecture.":[15],"An":[16],"assumption":[17],"the":[19,23,32,57,87,105,112,126,135],"is":[21,53],"that":[22,39],"system":[24],"has":[25],"already":[26],"been":[27],"partitioned":[28],"and":[29,86,116],"mapped":[30],"onto":[31],"appropriate":[33],"components":[34],"SoC":[37],"so":[38],"size":[40,82],"data":[42],"to":[43,104,125,140],"be":[44],"transferred":[45],"at":[46],"each":[47,61],"time":[48],"by":[49],"an":[50],"module":[52,62],"fixed.":[54],"We":[55],"model":[56],"communication":[58,67,106,148],"behavior":[59],"as":[63],"set":[65],"lifetime":[68],"intervals":[69],"(CLTIs),":[70],"which":[71,110],"are":[72,101],"optimized":[73,99],"in":[74,130],"terms":[75],"number":[77,89,113],"overlaps":[79],"among":[80],"them,":[81],"bus":[84],"width":[85],"minimum":[88],"buses,":[91],"using":[92],"ILP":[93],"(integer":[94],"linear":[95],"programming)":[96],"formulation.":[97],"These":[98],"CLTIs":[100],"later":[102],"given":[103],"algorithm,":[109],"gives":[111],"buses":[115],"their":[117],"interconnection.":[118],"The":[119],"results":[120],"applying":[122],"this":[123],"approach":[124],"Talking":[127],"Assistant":[128],"used":[129],"ubiquitous":[131],"computing":[132],"application":[133],"demonstrate":[134],"utility":[136],"our":[138],"techniques":[139],"synthesize":[141],"custom":[143],"multibus":[146],"architecture":[149],"complex":[152],"system.":[153]},"counts_by_year":[{"year":2018,"cited_by_count":1}],"updated_date":"2026-11-04T10:54:05.112534","created_date":"2016-06-24T00:00:00"}
