{"id":"https://openalex.org/W2128403399","doi":"https://doi.org/10.1109/fpl.2011.70","title":"Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System","display_name":"Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System","publication_year":2011,"publication_date":"2011-09-01","ids":{"openalex":"https://openalex.org/W2128403399","doi":"https://doi.org/10.1109/fpl.2011.70","mag":"2128403399"},"language":"en","primary_location":{"id":"doi:10.1109/fpl.2011.70","doi":"https://doi.org/10.1109/fpl.2011.70","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2011.70","pdf_url":null,"source":{"id":"https://openalex.org/S7407085929","display_name":"International Conference on Field Programmable Logic and Applications (FPL)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 21st International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://hdl.handle.net/1721.1/60266","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069200437","display_name":"Michel A. Kinsy","orcid":"https://orcid.org/0000-0002-1432-6939","observed_orcids":["https://orcid.org/0000-0002-1432-6939"]},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michel A. Kinsy","raw_affiliation_strings":["Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA, USA","[Dept. of Electr. Eng. & Comput. Sci., Massachusetts Inst. of Technol., Cambridge, MA, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA, USA","institution_ids":["https://openalex.org/I63966007"]},{"raw_affiliation_string":"[Dept. of Electr. Eng. & Comput. Sci., Massachusetts Inst. of Technol., Cambridge, MA, USA]","institution_ids":["https://openalex.org/I63966007"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009910914","display_name":"Michael Pellauer","orcid":"https://orcid.org/0000-0002-5305-4307","observed_orcids":["https://orcid.org/0000-0002-5305-4307"]},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michael Pellauer","raw_affiliation_strings":["Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA, USA","[Dept. of Electr. Eng. & Comput. Sci., Massachusetts Inst. of Technol., Cambridge, MA, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA, USA","institution_ids":["https://openalex.org/I63966007"]},{"raw_affiliation_string":"[Dept. of Electr. Eng. & Comput. Sci., Massachusetts Inst. of Technol., Cambridge, MA, USA]","institution_ids":["https://openalex.org/I63966007"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000525449","display_name":"Srinivas Devadas","orcid":"https://orcid.org/0000-0001-8253-7714","observed_orcids":["https://orcid.org/0000-0001-8253-7714"]},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Srinivas Devadas","raw_affiliation_strings":["Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA, USA","[Dept. of Electr. Eng. & Comput. Sci., Massachusetts Inst. of Technol., Cambridge, MA, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA, USA","institution_ids":["https://openalex.org/I63966007"]},{"raw_affiliation_string":"[Dept. of Electr. Eng. & Comput. Sci., Massachusetts Inst. of Technol., Cambridge, MA, USA]","institution_ids":["https://openalex.org/I63966007"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I63966007"],"apc_list":null,"apc_paid":null,"fwci":2.6084,"has_fulltext":false,"cited_by_count":35,"citation_normalized_percentile":{"value":0.90873947,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":93,"max":98},"biblio":{"volume":"5","issue":null,"first_page":"356","last_page":"362"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.649399995803833,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.649399995803833,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.3082999885082245,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.031599998474121094,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/heracles","display_name":"Heracles","score":0.7990000247955322},{"id":"https://openalex.org/keywords/multi-core-processors","display_name":"multi-core processors","score":0.8230000138282776},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.671999990940094},{"id":"https://openalex.org/keywords/fpga-synthesis","display_name":"FPGA synthesis","score":0.6520000100135803},{"id":"https://openalex.org/keywords/wormhole-routing","display_name":"wormhole routing","score":0.9599999785423279},{"id":"https://openalex.org/keywords/network-on-chip","display_name":"network-on-chip","score":0.8259999752044678},{"id":"https://openalex.org/keywords/distributed-shared-memory","display_name":"distributed shared memory","score":0.8019999861717224},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"memory hierarchy","score":0.6259999871253967},{"id":"https://openalex.org/keywords/pipelined-microprocessors","display_name":"pipelined microprocessors","score":0.7400000095367432},{"id":"https://openalex.org/keywords/open-source-hardware","display_name":"open-source hardware","score":0.5820000171661377}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8359712362289429},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.548547625541687},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5416972041130066},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.5130123496055603},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.511438250541687},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5030867457389832},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.499314546585083},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.47337931394577026},{"id":"https://openalex.org/C76399640","wikidata":"https://www.wikidata.org/wiki/Q189401","display_name":"Virtual memory","level":4,"score":0.45775046944618225},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.450194388628006},{"id":"https://openalex.org/C39528615","wikidata":"https://www.wikidata.org/wiki/Q1229610","display_name":"Distributed shared memory","level":5,"score":0.4271728992462158},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.4194728434085846},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.28461503982543945},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2521124482154846},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2505958378314972},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.2304944097995758},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.1663103997707367},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.14564621448516846}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/fpl.2011.70","doi":"https://doi.org/10.1109/fpl.2011.70","is_oa":false,"landing_page_url":"https://doi.org/10.1109/fpl.2011.70","pdf_url":null,"source":{"id":"https://openalex.org/S7407085929","display_name":"International Conference on Field Programmable Logic and Applications (FPL)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 21st International Conference on Field Programmable Logic and Applications","raw_type":"proceedings-article"},{"id":"pmh:oai:dspace.mit.edu:1721.1/60266","doi":null,"is_oa":true,"landing_page_url":"http://hdl.handle.net/1721.1/60266","pdf_url":null,"source":{"id":"https://openalex.org/S4306400425","display_name":"DSpace@MIT (Massachusetts Institute of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I63966007","host_organization_name":"Massachusetts Institute of Technology","host_organization_lineage":["https://openalex.org/I63966007"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc","license_id":"https://openalex.org/licenses/cc-by-nc","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":null}],"best_oa_location":{"id":"pmh:oai:dspace.mit.edu:1721.1/60266","doi":null,"is_oa":true,"landing_page_url":"http://hdl.handle.net/1721.1/60266","pdf_url":null,"source":{"id":"https://openalex.org/S4306400425","display_name":"DSpace@MIT (Massachusetts Institute of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I63966007","host_organization_name":"Massachusetts Institute of Technology","host_organization_lineage":["https://openalex.org/I63966007"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc","license_id":"https://openalex.org/licenses/cc-by-nc","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":null},"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":32,"referenced_works":["https://openalex.org/W1493456587","https://openalex.org/W1501077214","https://openalex.org/W1567646530","https://openalex.org/W1582084802","https://openalex.org/W1979418125","https://openalex.org/W2042876290","https://openalex.org/W2088661064","https://openalex.org/W2097560795","https://openalex.org/W2099399959","https://openalex.org/W2101221491","https://openalex.org/W2108436158","https://openalex.org/W2118681606","https://openalex.org/W2123184444","https://openalex.org/W2127194995","https://openalex.org/W2128452435","https://openalex.org/W2129919720","https://openalex.org/W2130853508","https://openalex.org/W2136084694","https://openalex.org/W2140894580","https://openalex.org/W2147291108","https://openalex.org/W2148323349","https://openalex.org/W2154323564","https://openalex.org/W2158734177","https://openalex.org/W2160642395","https://openalex.org/W2162788247","https://openalex.org/W2994857926","https://openalex.org/W3143675127","https://openalex.org/W4240575514","https://openalex.org/W4242669587","https://openalex.org/W4243513274","https://openalex.org/W6629592042","https://openalex.org/W7074686048"],"related_works":["https://openalex.org/W2151925011","https://openalex.org/W6991435236","https://openalex.org/W2307985327","https://openalex.org/W2000001288","https://openalex.org/W3214420819","https://openalex.org/W2101136179","https://openalex.org/W2073889623","https://openalex.org/W2137385009","https://openalex.org/W3131821736","https://openalex.org/W2843218423"],"abstract_inverted_index":{"Heracles":[0,98],"is":[1,11,52,74,120],"an":[2],"open-source":[3],"complete":[4],"multicore":[5],"system":[6,96],"written":[7],"in":[8,97,166],"Verilog.":[9],"It":[10],"fully":[12,30],"parameterized":[13],"and":[14,18,23,44,64,82,144],"can":[15,99],"be":[16,100],"reconfigured":[17],"synthesized":[19],"into":[20],"different":[21,138],"topologies":[22],"sizes.":[24],"Each":[25,118],"processing":[26],"node":[27],"has":[28],"a":[29,39,45,131,158],"bypassed,":[31],"7-stage":[32],"pipelined":[33],"microprocessor":[34,73],"running":[35],"the":[36,59,61,65,69,72,90,123,126,142,149],"MIPS-III":[37],"ISA,":[38],"4-stage":[40],"input-buffer,":[41],"virtual-channel":[42],"router,":[43],"local":[46],"variable-size":[47],"shared":[48,106,111],"memory.":[49],"Our":[50],"design":[51],"highly":[53],"modular":[54],"with":[55],"clear":[56],"interfaces":[57],"between":[58],"core,":[60],"memory":[62,92,95,107,112],"hierarchy,":[63],"on-chip":[66],"network.":[67],"In":[68],"baseline":[70],"design,":[71],"attached":[75],"to":[76,89,122,164],"two":[77],"caches,":[78],"one":[79,83,103],"instruction":[80],"cache":[81],"data":[84],"cache,":[85],"which":[86],"are":[87],"oblivious":[88],"global":[91,105],"organization.":[93],"The":[94],"configured":[101],"as":[102],"single":[104],"(SM),":[108],"or":[109,114],"distributed":[110],"(DSM),":[113],"any":[115],"combination":[116],"thereof.":[117],"core":[119],"connected":[121],"rest":[124],"of":[125,128,141],"network":[127],"processors":[129],"by":[130],"parameterized,":[132],"realistic,":[133],"wormhole":[134],"router.":[135],"We":[136,155],"show":[137],"topology":[139],"configurations":[140],"system,":[143],"their":[145],"synthesis":[146],"results":[147],"on":[148],"Xilinx":[150],"Virtex-5":[151],"LX330T":[152],"FPGA":[153],"board.":[154],"also":[156],"provide":[157],"small":[159],"MIPS":[160],"cross-compiler":[161],"tool":[162],"chain":[163],"assist":[165],"developing":[167],"software":[168],"for":[169],"Heracles.":[170]},"counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":3},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":6},{"year":2013,"cited_by_count":6},{"year":2012,"cited_by_count":2}],"updated_date":"2026-11-07T11:25:07.637180","created_date":"2016-06-24T00:00:00"}