{"id":"https://openalex.org/W2124646838","doi":"https://doi.org/10.1109/iccd.1997.628904","title":"Asynchronous transpose-matrix architectures","display_name":"Asynchronous transpose-matrix architectures","publication_year":1997,"publication_date":"1997-01-01","ids":{"openalex":"https://openalex.org/W2124646838","doi":"https://doi.org/10.1109/iccd.1997.628904","mag":"2124646838"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.1997.628904","doi":"https://doi.org/10.1109/iccd.1997.628904","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.1997.628904","pdf_url":null,"source":{"id":"https://openalex.org/S4210174938","display_name":"IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD)","issn_l":"1063-6404","issn":["1063-6404","2576-6996"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":["jufo-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings International Conference on Computer Design VLSI in Computers and Processors","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110228319","display_name":"J. Tierno","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4210114115","display_name":"IBM Research - Thomas J. Watson Research Center","ror":"https://ror.org/0265w5591","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J.A. Tierno","raw_affiliation_strings":["IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA","IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA","institution_ids":["https://openalex.org/I4210114115"]},{"raw_affiliation_string":"IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA","institution_ids":["https://openalex.org/I4210114115"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5080747890","display_name":"Prabhakar N. Kudva","orcid":"https://orcid.org/0000-0003-0854-8612","observed_orcids":["https://orcid.org/0000-0003-0854-8612"]},"institutions":[{"id":"https://openalex.org/I4210114115","display_name":"IBM Research - Thomas J. Watson Research Center","ror":"https://ror.org/0265w5591","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"P. Kudva","raw_affiliation_strings":["IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA","institution_ids":["https://openalex.org/I4210114115"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210114115"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.35498255,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"423","last_page":"428"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.7759000062942505,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.7759000062942505,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.07029999792575836,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.0333000011742115,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/matrix-transposition","display_name":"matrix transposition","score":0.9160000085830688},{"id":"https://openalex.org/keywords/asynchronous-circuits","display_name":"asynchronous circuits","score":0.8309999704360962},{"id":"https://openalex.org/keywords/discrete-cosine-transform","display_name":"discrete cosine transform","score":0.906000018119812},{"id":"https://openalex.org/keywords/image-and-video-compression","display_name":"image and video compression","score":0.7379999756813049},{"id":"https://openalex.org/keywords/power-dissipation","display_name":"power dissipation","score":0.765999972820282},{"id":"https://openalex.org/keywords/latency","display_name":"latency","score":0.878000020980835},{"id":"https://openalex.org/keywords/distributed-arithmetic","display_name":"distributed arithmetic","score":0.5139999985694885}],"concepts":[{"id":"https://openalex.org/C200106649","wikidata":"https://www.wikidata.org/wiki/Q223683","display_name":"Transpose","level":3,"score":0.9322584271430969},{"id":"https://openalex.org/C2221639","wikidata":"https://www.wikidata.org/wiki/Q2877","display_name":"Discrete cosine transform","level":3,"score":0.778759241104126},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7740305662155151},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.6048377752304077},{"id":"https://openalex.org/C17349429","wikidata":"https://www.wikidata.org/wiki/Q1049914","display_name":"Matrix multiplication","level":3,"score":0.4368467926979065},{"id":"https://openalex.org/C78548338","wikidata":"https://www.wikidata.org/wiki/Q2493","display_name":"Data compression","level":2,"score":0.4326745271682739},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.41905418038368225},{"id":"https://openalex.org/C42355184","wikidata":"https://www.wikidata.org/wiki/Q1361088","display_name":"Matrix decomposition","level":3,"score":0.414757639169693},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.41475486755371094},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.39073941111564636},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3232572078704834},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.1507503092288971},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.09856095910072327},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C84114770","wikidata":"https://www.wikidata.org/wiki/Q46344","display_name":"Quantum","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C158693339","wikidata":"https://www.wikidata.org/wiki/Q190524","display_name":"Eigenvalues and eigenvectors","level":2,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.1997.628904","doi":"https://doi.org/10.1109/iccd.1997.628904","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.1997.628904","pdf_url":null,"source":{"id":"https://openalex.org/S4210174938","display_name":"IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD)","issn_l":"1063-6404","issn":["1063-6404","2576-6996"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":["jufo-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings International Conference on Computer Design VLSI in Computers and Processors","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2029005287","https://openalex.org/W2031614119","https://openalex.org/W2115907784","https://openalex.org/W2167942214","https://openalex.org/W2168369380","https://openalex.org/W4231905827"],"related_works":["https://openalex.org/W1945396510","https://openalex.org/W1911567611","https://openalex.org/W2060530641","https://openalex.org/W2143092926","https://openalex.org/W4240837482","https://openalex.org/W4378977140","https://openalex.org/W2121002498","https://openalex.org/W2119361478","https://openalex.org/W7104758740","https://openalex.org/W7099294132"],"abstract_inverted_index":{"The":[0,50],"matrix":[1,68],"transposition":[2],"operation":[3],"is":[4,57],"a":[5,42],"necessary":[6],"step":[7],"in":[8,15,91,100],"several":[9],"image/video":[10],"compression":[11],"and":[12,22,26,40,60,95,112],"decompression":[13],"algorithms,":[14],"particular":[16],"the":[17,54,88,106,114],"discrete":[18],"cosine":[19],"transform":[20],"(DCT)":[21],"its":[23],"inverse":[24],"(IDCT),":[25],"some":[27],"distributed":[28],"arithmetic":[29],"applications.":[30,49],"These":[31,70],"algorithms":[32],"have":[33,84],"to":[34],"be":[35],"performed":[36],"at":[37,97],"high":[38],"data-rates,":[39],"with":[41],"minimum":[43],"of":[44,93,108,117],"power":[45],"dissipation":[46],"for":[47],"portable":[48],"authors":[51],"describe":[52],"how":[53],"clocked":[55,89],"solution":[56,90],"usually":[58],"implemented,":[59],"present":[61],"two":[62,75],"new":[63],"asynchronous":[64],"architectures":[65,111],"that":[66],"perform":[67],"transposition.":[69],"architectures,":[71],"one":[72,78],"based":[73,79],"on":[74,80],"phase":[76,82],"signaling,":[77,83],"four":[81],"better":[85],"characteristics":[86,107],"than":[87],"terms":[92],"latency":[94],"power,":[96],"no":[98],"cost":[99],"area":[101],"or":[102],"throughput.":[103],"They":[104],"discuss":[105],"these":[109],"three":[110],"evaluate":[113],"relative":[115],"advantages":[116],"each":[118],"one.":[119]},"counts_by_year":[],"updated_date":"2026-10-26T11:51:55.731654","created_date":"2016-06-24T00:00:00"}