{"id":"https://openalex.org/W2115166483","doi":"https://doi.org/10.1109/iccad.1990.129908","title":"Feedback-driven datapath optimization in Fasolt","display_name":"Feedback-driven datapath optimization in Fasolt","publication_year":2002,"publication_date":"2002-12-04","ids":{"openalex":"https://openalex.org/W2115166483","doi":"https://doi.org/10.1109/iccad.1990.129908","mag":"2115166483"},"language":"en","primary_location":{"id":"doi:10.1109/iccad.1990.129908","doi":"https://doi.org/10.1109/iccad.1990.129908","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.1990.129908","pdf_url":null,"source":{"id":"https://openalex.org/S4306419226","display_name":"International Conference on Computer Aided Design","issn_l":"1933-7760","issn":["1933-7760"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":["jufo-1"],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5114008661","display_name":"D.W. Knapp","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"D.W. Knapp","raw_affiliation_strings":["University of Illinois, Urbana, IL, USA","Illinois Univ., Urbana, IL, , USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Illinois, Urbana, IL, USA","institution_ids":["https://openalex.org/I157725225"]},{"raw_affiliation_string":"Illinois Univ., Urbana, IL, , USA","institution_ids":["https://openalex.org/I157725225"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5114008661"],"corresponding_institution_ids":["https://openalex.org/I157725225"],"apc_list":null,"apc_paid":null,"fwci":1.8772,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.85461081,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"2","issue":null,"first_page":"300","last_page":"303"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.8324999809265137,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.8324999809265137,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.15970000624656677,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.003700000001117587,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/feedback-driven-optimization","display_name":"feedback-driven optimization","score":0.9559999704360962},{"id":"https://openalex.org/keywords/layout-information","display_name":"layout information","score":0.7009999752044678},{"id":"https://openalex.org/keywords/retiming","display_name":"retiming","score":0.9549999833106995},{"id":"https://openalex.org/keywords/critical-path","display_name":"critical path","score":0.7710000276565552},{"id":"https://openalex.org/keywords/channel-density","display_name":"channel density","score":0.996999979019165}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.944010853767395},{"id":"https://openalex.org/C41112130","wikidata":"https://www.wikidata.org/wiki/Q2146175","display_name":"Retiming","level":2,"score":0.9194415807723999},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7274599671363831},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5563604831695557},{"id":"https://openalex.org/C96147967","wikidata":"https://www.wikidata.org/wiki/Q190686","display_name":"Subroutine","level":2,"score":0.5416756868362427},{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.5401188135147095},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.49642878770828247},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.48226791620254517},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.46200060844421387},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.4325312674045563},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.43030187487602234},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.34700706601142883},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2649638056755066},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.2359858751296997},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.2281900942325592},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.18535634875297546},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.12174525856971741}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccad.1990.129908","doi":"https://doi.org/10.1109/iccad.1990.129908","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.1990.129908","pdf_url":null,"source":{"id":"https://openalex.org/S4306419226","display_name":"International Conference on Computer Aided Design","issn_l":"1933-7760","issn":["1933-7760"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":["jufo-1"],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1980746862","https://openalex.org/W1997875187","https://openalex.org/W2060342326","https://openalex.org/W2064328314","https://openalex.org/W2118113314","https://openalex.org/W2163205571","https://openalex.org/W4230773133","https://openalex.org/W4233466666","https://openalex.org/W4237758281","https://openalex.org/W4243349038","https://openalex.org/W4243351237","https://openalex.org/W4245962916"],"related_works":["https://openalex.org/W4231327449","https://openalex.org/W2160020444","https://openalex.org/W2144525089","https://openalex.org/W6998820367","https://openalex.org/W2397504591","https://openalex.org/W2312166864","https://openalex.org/W2183286342","https://openalex.org/W1608848694","https://openalex.org/W4251976285","https://openalex.org/W1517141392"],"abstract_inverted_index":{"Fasolt":[0,10,40],"is":[1,11,28],"a":[2,6,71],"program":[3],"that":[4,14],"optimizes":[5],"register-level":[7],"datapath":[8],"design.":[9],"unique":[12],"in":[13,70,85],"it":[15,27,31],"uses":[16,32,42],"layout":[17],"information":[18,34],"to":[19,35,48,54,78],"drive":[20,36],"the":[21],"choice":[22],"of":[23,51],"optimizing":[24],"transformations;":[25],"hence":[26],"feedback-driven,":[29],"because":[30],"low-level":[33],"high-level":[37],"decision":[38],"making.":[39],"1.0":[41],"critical":[43],"path":[44],"and":[45,63,81],"channel":[46],"density":[47],"select":[49],"pairs":[50],"wire":[52],"bundles":[53],"be":[55],"merged,":[56],"which":[57,74],"may":[58],"necessitate":[59],"retiming.":[60],"Hence":[61],"scheduling":[62],"allocation":[64],"can":[65],"take":[66],"wiring":[67],"into":[68],"account":[69],"novel":[72],"way,":[73],"has":[75],"been":[76],"sufficient":[77],"given":[79],"10":[80],"50%":[82],"area":[83],"reductions":[84],"naive":[86],"initial":[87],"designs.>":[88]},"counts_by_year":[],"updated_date":"2026-11-04T10:54:05.112534","created_date":"2016-06-24T00:00:00"}
