{"id":"https://openalex.org/W2110658287","doi":"https://doi.org/10.1109/vlsit.2010.5556116","title":"Minimization of threshold voltage variation to AVT=1.3mV\u00b5m in bulk high-k/metal gated devices by dopant-diffusion control using integrated FSP-FLA technology","display_name":"Minimization of threshold voltage variation to AVT=1.3mV\u00b5m in bulk high-k/metal gated devices by dopant-diffusion control using integrated FSP-FLA technology","publication_year":2010,"publication_date":"2010-06-01","ids":{"openalex":"https://openalex.org/W2110658287","doi":"https://doi.org/10.1109/vlsit.2010.5556116","mag":"2110658287"},"language":"en","primary_location":{"id":"doi:10.1109/vlsit.2010.5556116","doi":"https://doi.org/10.1109/vlsit.2010.5556116","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsit.2010.5556116","pdf_url":null,"source":{"id":"https://openalex.org/S4306421008","display_name":"Symposium on VLSI Technology","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Symposium on VLSI Technology","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100993521","display_name":"Shinichi Kato","orcid":"https://orcid.org/0000-0002-5236-0548","observed_orcids":["https://orcid.org/0000-0002-5236-0548"]},"institutions":[{"id":"https://openalex.org/I4405276234","display_name":"Semiconductor Leading Edge Technologies, Inc (Japan)","ror":"https://ror.org/0523jgb37","country_code":"JP","type":"company","lineage":["https://openalex.org/I4405276234"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Shinichi Kato","raw_affiliation_strings":["Semiconductor Leading Edge Technologies, Inc., Tsukuba, Ibaraki, Japan","Semiconductor Leading Edge Technologies Inc. (Selete), 16-1 Onogawa, 305-8569 Tsukuba, Ibaraki, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Semiconductor Leading Edge Technologies, Inc., Tsukuba, Ibaraki, Japan","institution_ids":["https://openalex.org/I4405276234"]},{"raw_affiliation_string":"Semiconductor Leading Edge Technologies Inc. (Selete), 16-1 Onogawa, 305-8569 Tsukuba, Ibaraki, Japan","institution_ids":["https://openalex.org/I4405276234"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077505445","display_name":"Takayuki Aoyama","orcid":"https://orcid.org/0000-0002-8841-6697","observed_orcids":["https://orcid.org/0000-0002-8841-6697"]},"institutions":[{"id":"https://openalex.org/I4405276234","display_name":"Semiconductor Leading Edge Technologies, Inc (Japan)","ror":"https://ror.org/0523jgb37","country_code":"JP","type":"company","lineage":["https://openalex.org/I4405276234"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Takayuki Aoyama","raw_affiliation_strings":["Semiconductor Leading Edge Technologies, Inc., Tsukuba, Ibaraki, Japan","Semiconductor Leading Edge Technologies Inc. (Selete), 16-1 Onogawa, 305-8569 Tsukuba, Ibaraki, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Semiconductor Leading Edge Technologies, Inc., Tsukuba, Ibaraki, Japan","institution_ids":["https://openalex.org/I4405276234"]},{"raw_affiliation_string":"Semiconductor Leading Edge Technologies Inc. (Selete), 16-1 Onogawa, 305-8569 Tsukuba, Ibaraki, Japan","institution_ids":["https://openalex.org/I4405276234"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038657464","display_name":"Takashi Onizawa","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4405276234","display_name":"Semiconductor Leading Edge Technologies, Inc (Japan)","ror":"https://ror.org/0523jgb37","country_code":"JP","type":"company","lineage":["https://openalex.org/I4405276234"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Takashi Onizawa","raw_affiliation_strings":["Semiconductor Leading Edge Technologies, Inc., Tsukuba, Ibaraki, Japan","Semiconductor Leading Edge Technologies Inc. (Selete), 16-1 Onogawa, 305-8569 Tsukuba, Ibaraki, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Semiconductor Leading Edge Technologies, Inc., Tsukuba, Ibaraki, Japan","institution_ids":["https://openalex.org/I4405276234"]},{"raw_affiliation_string":"Semiconductor Leading Edge Technologies Inc. (Selete), 16-1 Onogawa, 305-8569 Tsukuba, Ibaraki, Japan","institution_ids":["https://openalex.org/I4405276234"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111402044","display_name":"Kazuto Ikeda","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4405276234","display_name":"Semiconductor Leading Edge Technologies, Inc (Japan)","ror":"https://ror.org/0523jgb37","country_code":"JP","type":"company","lineage":["https://openalex.org/I4405276234"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kazuto Ikeda","raw_affiliation_strings":["Semiconductor Leading Edge Technologies, Inc., Tsukuba, Ibaraki, Japan","Semiconductor Leading Edge Technologies Inc. (Selete), 16-1 Onogawa, 305-8569 Tsukuba, Ibaraki, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Semiconductor Leading Edge Technologies, Inc., Tsukuba, Ibaraki, Japan","institution_ids":["https://openalex.org/I4405276234"]},{"raw_affiliation_string":"Semiconductor Leading Edge Technologies Inc. (Selete), 16-1 Onogawa, 305-8569 Tsukuba, Ibaraki, Japan","institution_ids":["https://openalex.org/I4405276234"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109357251","display_name":"Yuzuru Ohji","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4405276234","display_name":"Semiconductor Leading Edge Technologies, Inc (Japan)","ror":"https://ror.org/0523jgb37","country_code":"JP","type":"company","lineage":["https://openalex.org/I4405276234"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yuzuru Ohji","raw_affiliation_strings":["Semiconductor Leading Edge Technologies, Inc., Tsukuba, Ibaraki, Japan","Semiconductor Leading Edge Technologies Inc. (Selete), 16-1 Onogawa, 305-8569 Tsukuba, Ibaraki, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Semiconductor Leading Edge Technologies, Inc., Tsukuba, Ibaraki, Japan","institution_ids":["https://openalex.org/I4405276234"]},{"raw_affiliation_string":"Semiconductor Leading Edge Technologies Inc. (Selete), 16-1 Onogawa, 305-8569 Tsukuba, Ibaraki, Japan","institution_ids":["https://openalex.org/I4405276234"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4405276234"],"apc_list":null,"apc_paid":null,"fwci":0.4269,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.46644755,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":88,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"71","last_page":"72"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.7235999703407288,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.7235999703407288,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.21580000221729279,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.017999999225139618,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/threshold-voltage-variation","display_name":"threshold voltage variation","score":0.9869999885559082},{"id":"https://openalex.org/keywords/random-dopant-fluctuation","display_name":"random dopant fluctuation","score":0.9649999737739563},{"id":"https://openalex.org/keywords/pattern-effect","display_name":"pattern effect","score":0.8840000033378601},{"id":"https://openalex.org/keywords/flash-lamp-annealing","display_name":"flash lamp annealing","score":0.625},{"id":"https://openalex.org/keywords/high-k-metal-gate-stack","display_name":"high-k/metal gate stack","score":0.8289999961853027},{"id":"https://openalex.org/keywords/bulk-mosfet","display_name":"bulk MOSFET","score":0.4740000069141388}],"concepts":[{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.9630408883094788},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.9187839031219482},{"id":"https://openalex.org/C191952053","wikidata":"https://www.wikidata.org/wiki/Q15119237","display_name":"Dopant","level":3,"score":0.6823984384536743},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.5681759715080261},{"id":"https://openalex.org/C69357855","wikidata":"https://www.wikidata.org/wiki/Q163214","display_name":"Diffusion","level":2,"score":0.5449553728103638},{"id":"https://openalex.org/C195370968","wikidata":"https://www.wikidata.org/wiki/Q1754002","display_name":"Threshold voltage","level":4,"score":0.45499521493911743},{"id":"https://openalex.org/C51140833","wikidata":"https://www.wikidata.org/wiki/Q6822740","display_name":"Metal gate","level":5,"score":0.42152321338653564},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.378953218460083},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.36205393075942993},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3612958788871765},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3537970185279846},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.24903345108032227},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14849919080734253},{"id":"https://openalex.org/C57863236","wikidata":"https://www.wikidata.org/wiki/Q1130571","display_name":"Doping","level":2,"score":0.1337200105190277},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.11122262477874756},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.09058594703674316},{"id":"https://openalex.org/C2361726","wikidata":"https://www.wikidata.org/wiki/Q5527031","display_name":"Gate oxide","level":4,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsit.2010.5556116","doi":"https://doi.org/10.1109/vlsit.2010.5556116","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsit.2010.5556116","pdf_url":null,"source":{"id":"https://openalex.org/S4306421008","display_name":"Symposium on VLSI Technology","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Symposium on VLSI Technology","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W2002057511"],"related_works":["https://openalex.org/W2115483974","https://openalex.org/W2599302359","https://openalex.org/W2133324285","https://openalex.org/W1584306300","https://openalex.org/W2124251489","https://openalex.org/W2147198131","https://openalex.org/W2331677695","https://openalex.org/W3143810590","https://openalex.org/W2037403496","https://openalex.org/W3149249597"],"abstract_inverted_index":{"We":[0,44],"have":[1],"successfully":[2],"suppressed":[3],"threshold":[4],"voltage":[5],"variations":[6],"due":[7],"to":[8,77],"pattern":[9,27],"effect":[10,28],"problems":[11],"and":[12,100],"random":[13],"dopant":[14],"fluctuation":[15],"(RDF)":[16],"using":[17,35],"an":[18],"integrated":[19],"FSP-FLA":[20],"technology.":[21],"The":[22],"serious":[23],"problem":[24],"of":[25,69,74],"the":[26,46,57,66,72,78],"in":[29,49],"FLA":[30,70],"can":[31],"be":[32],"solved":[33],"by":[34],"a":[36,90],"light-absorber":[37],"carbon":[38],"film":[39],"process,":[40],"together":[41],"with":[42,61,82],"FSP-FLA.":[43],"estimated":[45],"temperature":[47],"range":[48],"our":[50],"test":[51],"chip":[52],"was":[53],"within":[54],"10\u00b0C,":[55],"being":[56],"same":[58,79],"level":[59,80],"obtained":[60],"spike":[62],"RTA.":[63],"In":[64],"addition,":[65],"diffusion-less":[67],"feature":[68],"reduces":[71],"RDF":[73],"NMOS":[75,99],"down":[76],"as":[81],"PMOS.":[83,103],"By":[84],"applying":[85],"several":[86],"optimized":[87],"processes,":[88],"including":[89],"high-k/metal":[91],"gate":[92],"stack,":[93],"we":[94],"achieved":[95],"AVTas":[96],"1.3mV\u03bcm":[97],"for":[98,102],"1.2mV\u03bcm":[101]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-10-05T09:50:58.205359","created_date":"2016-06-24T00:00:00"}
