{"id":"https://openalex.org/W2107429935","doi":"https://doi.org/10.1109/tcad.2003.816219","title":"Rigorous integration of semiconductor process and device simulators","display_name":"Rigorous integration of semiconductor process and device simulators","publication_year":2003,"publication_date":"2003-09-01","ids":{"openalex":"https://openalex.org/W2107429935","doi":"https://doi.org/10.1109/tcad.2003.816219","mag":"2107429935"},"language":"en","primary_location":{"id":"doi:10.1109/tcad.2003.816219","doi":"https://doi.org/10.1109/tcad.2003.816219","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2003.816219","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["ccf-a","cwts-core","dongbi-a","jufo-2","norway-1","poland-100","russia-white-list-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"},"volume":null,"type":"article","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007828638","display_name":"Thomas M. Binder","orcid":"https://orcid.org/0000-0001-8244-1798","observed_orcids":["https://orcid.org/0000-0001-8244-1798"]},"institutions":[{"id":"https://openalex.org/I145847075","display_name":"TU Wien","ror":"https://ror.org/04d836q62","country_code":"AT","type":"education","lineage":["https://openalex.org/I145847075"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"T. Binder","raw_affiliation_strings":["Institute for Microelectronics, Technical University of of Vienna, Vienna, Austria","Inst. for Microelectron., Tech. Univ. of Vienna, Austria#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute for Microelectronics, Technical University of of Vienna, Vienna, Austria","institution_ids":["https://openalex.org/I145847075"]},{"raw_affiliation_string":"Inst. for Microelectron., Tech. Univ. of Vienna, Austria#TAB#","institution_ids":["https://openalex.org/I145847075"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072452255","display_name":"Andreas H\u00f6ssinger","orcid":"https://orcid.org/0000-0002-8949-1680","observed_orcids":["https://orcid.org/0000-0002-8949-1680"]},"institutions":[{"id":"https://openalex.org/I145847075","display_name":"TU Wien","ror":"https://ror.org/04d836q62","country_code":"AT","type":"education","lineage":["https://openalex.org/I145847075"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"A. Hossinger","raw_affiliation_strings":["Institute for Microelectronics, Technical University of of Vienna, Vienna, Austria","Inst. for Microelectron., Tech. Univ. of Vienna, Austria#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute for Microelectronics, Technical University of of Vienna, Vienna, Austria","institution_ids":["https://openalex.org/I145847075"]},{"raw_affiliation_string":"Inst. for Microelectron., Tech. Univ. of Vienna, Austria#TAB#","institution_ids":["https://openalex.org/I145847075"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043510129","display_name":"S. Selberherr","orcid":"https://orcid.org/0000-0002-5583-6177","observed_orcids":["https://orcid.org/0000-0002-5583-6177"]},"institutions":[{"id":"https://openalex.org/I145847075","display_name":"TU Wien","ror":"https://ror.org/04d836q62","country_code":"AT","type":"education","lineage":["https://openalex.org/I145847075"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"S. Selberherr","raw_affiliation_strings":["Institute for Microelectronics, Technical University of of Vienna, Vienna, Austria","Inst. for Microelectron., Tech. Univ. of Vienna, Austria#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute for Microelectronics, Technical University of of Vienna, Vienna, Austria","institution_ids":["https://openalex.org/I145847075"]},{"raw_affiliation_string":"Inst. for Microelectron., Tech. Univ. of Vienna, Austria#TAB#","institution_ids":["https://openalex.org/I145847075"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I145847075"],"apc_list":{"value":2645,"currency":"USD","value_usd":2645},"apc_paid":null,"fwci":1.306,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.79436515,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":87,"max":93},"biblio":{"volume":"22","issue":"9","first_page":"1204","last_page":"1214"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.4207000136375427,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.4207000136375427,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.3837999999523163,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11159","display_name":"Manufacturing Process and Optimization","score":0.017799999564886093,"subfield":{"id":"https://openalex.org/subfields/2209","display_name":"Industrial and Manufacturing Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/semiconductor-process-simulation","display_name":"semiconductor process simulation","score":0.8069999814033508},{"id":"https://openalex.org/keywords/device-simulation","display_name":"device simulation","score":0.7110000252723694},{"id":"https://openalex.org/keywords/object-oriented-data-model","display_name":"object-oriented data model","score":0.8899999856948853},{"id":"https://openalex.org/keywords/3d-simulation","display_name":"three-dimensional simulation","score":0.7450000047683716},{"id":"https://openalex.org/keywords/topography-simulation","display_name":"topography simulation","score":0.9760000109672546}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7573868036270142},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.6755616664886475},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.6517266035079956},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.5956641435623169},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.49238884449005127},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.48335689306259155},{"id":"https://openalex.org/C15845906","wikidata":"https://www.wikidata.org/wiki/Q1172338","display_name":"Data exchange","level":2,"score":0.48288631439208984},{"id":"https://openalex.org/C100463513","wikidata":"https://www.wikidata.org/wiki/Q5227322","display_name":"Data model (GIS)","level":2,"score":0.4741508364677429},{"id":"https://openalex.org/C67186912","wikidata":"https://www.wikidata.org/wiki/Q367664","display_name":"Data modeling","level":2,"score":0.4598667621612549},{"id":"https://openalex.org/C2781238097","wikidata":"https://www.wikidata.org/wiki/Q175026","display_name":"Object (grammar)","level":2,"score":0.4559609591960907},{"id":"https://openalex.org/C131584629","wikidata":"https://www.wikidata.org/wiki/Q4308705","display_name":"Coupling (piping)","level":2,"score":0.4541934132575989},{"id":"https://openalex.org/C160671074","wikidata":"https://www.wikidata.org/wiki/Q267131","display_name":"Wafer","level":2,"score":0.44899293780326843},{"id":"https://openalex.org/C44154836","wikidata":"https://www.wikidata.org/wiki/Q45045","display_name":"Simulation","level":1,"score":0.3408232033252716},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.325905978679657},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.2909258008003235},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1337103545665741},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.12827399373054504},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.11649137735366821},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.10946351289749146},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.08545026183128357},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcad.2003.816219","doi":"https://doi.org/10.1109/tcad.2003.816219","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcad.2003.816219","pdf_url":null,"source":{"id":"https://openalex.org/S100835903","display_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","issn_l":"0278-0070","issn":["0278-0070","1937-4151"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["ccf-a","cwts-core","dongbi-a","jufo-2","norway-1","poland-100","russia-white-list-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W581144","https://openalex.org/W36052677","https://openalex.org/W176970915","https://openalex.org/W1495128907","https://openalex.org/W1590057361","https://openalex.org/W1639139368","https://openalex.org/W1924807040","https://openalex.org/W2043060552","https://openalex.org/W2063135141","https://openalex.org/W2080351843","https://openalex.org/W2107595716","https://openalex.org/W2129412583","https://openalex.org/W2133165322","https://openalex.org/W2159612597","https://openalex.org/W2161999941","https://openalex.org/W2219433894","https://openalex.org/W3160920738","https://openalex.org/W4250064880"],"related_works":["https://openalex.org/W1983278959","https://openalex.org/W7043946743","https://openalex.org/W2125536084","https://openalex.org/W1989134960","https://openalex.org/W2743600301","https://openalex.org/W1549178426","https://openalex.org/W2039384871","https://openalex.org/W24214158","https://openalex.org/W2187316470","https://openalex.org/W1927813018"],"abstract_inverted_index":{"We":[0],"deal":[1],"with":[2],"problems":[3],"arising":[4],"in":[5,64,122,141],"the":[6,50,65,72,75,130],"coupling":[7,66],"of":[8,18,29,58,67,95,98,137],"process":[9,46,88,126],"and":[10,20,47,89,101,104],"device":[11,48,90],"simulators.":[12,91],"It":[13,92],"is":[14,36,53,93,139],"analyzed":[15],"what":[16],"kind":[17],"data":[19,34,41,79,84,110,132],"algorithms":[21,114],"such":[22],"simulations":[23],"are":[24,69],"based":[25,128],"on.":[26],"An":[27],"overview":[28],"existing":[30,87],"technology":[31],"computer-aided":[32],"design":[33],"models":[35],"given.":[37],"A":[38],"generic":[39],"object-oriented":[40,59],"model":[42,80,111,133],"suitable":[43],"for":[44],"three-dimensional":[45],"simulations,":[49],"so-called":[51],"WAFER-STATE-SERVER":[52],"presented.":[54],"By":[55],"taking":[56],"advantage":[57],"abstraction":[60],"mechanisms,":[61],"key":[62],"tasks":[63],"simulators":[68,127],"relocated":[70],"from":[71],"simulator":[73],"into":[74],"WAFER-STATE-SERVER.":[76],"The":[77,109],"new":[78,131],"allows":[81],"an":[82],"efficient":[83],"exchange":[85],"between":[86],"capable":[94],"managing":[96],"geometries":[97],"different":[99],"dimensions,":[100],"handling":[102],"grids":[103],"distributed":[105],"quantities":[106],"stored":[107],"therein.":[108],"also":[112],"defines":[113],"to":[115],"perform":[116],"geometrical":[117],"operations":[118],"as":[119],"they":[120],"occur":[121],"topography":[123],"simulations.":[124],"Three":[125],"on":[129],"were":[134],"developed,":[135],"one":[136],"which":[138],"presented":[140],"this":[142],"work.":[143]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2026-11-12T12:28:57.059296","created_date":"2016-06-24T00:00:00"}