{"id":"https://openalex.org/W2107299528","doi":"https://doi.org/10.1109/vlsic.2010.5560277","title":"A 2Tb/s 6\u00d74 mesh network with DVFS and 2.3Tb/s/W router in 45nm CMOS","display_name":"A 2Tb/s 6\u00d74 mesh network with DVFS and 2.3Tb/s/W router in 45nm CMOS","publication_year":2010,"publication_date":"2010-06-01","ids":{"openalex":"https://openalex.org/W2107299528","doi":"https://doi.org/10.1109/vlsic.2010.5560277","mag":"2107299528"},"language":"en","primary_location":{"id":"doi:10.1109/vlsic.2010.5560277","doi":"https://doi.org/10.1109/vlsic.2010.5560277","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsic.2010.5560277","pdf_url":null,"source":{"id":"https://openalex.org/S4393918263","display_name":"Symposium on VLSI Circuits","issn_l":"2166-9600","issn":["2166-9600"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":["jufo-1"],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Symposium on VLSI Circuits","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5077422345","display_name":"Praveen Salihundam","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN","US"],"is_corresponding":false,"raw_author_name":"Praveen Salihundam","raw_affiliation_strings":["Microprocessor Research, Intel Laboratories, Intel Corporation, Bangalore, India","Microprocessor Research, Intel Labs, Intel Corporation, Bangalore, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Research, Intel Laboratories, Intel Corporation, Bangalore, India","institution_ids":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]},{"raw_affiliation_string":"Microprocessor Research, Intel Labs, Intel Corporation, Bangalore, India","institution_ids":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Shailendra Jain","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN","US"],"is_corresponding":false,"raw_author_name":"Shailendra Jain","raw_affiliation_strings":["Microprocessor Research, Intel Laboratories, Intel Corporation, Bangalore, India","Microprocessor Research, Intel Labs, Intel Corporation, Bangalore, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Research, Intel Laboratories, Intel Corporation, Bangalore, India","institution_ids":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]},{"raw_affiliation_string":"Microprocessor Research, Intel Labs, Intel Corporation, Bangalore, India","institution_ids":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112441360","display_name":"Tiju Jacob","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN","US"],"is_corresponding":false,"raw_author_name":"Tiju Jacob","raw_affiliation_strings":["Microprocessor Research, Intel Laboratories, Intel Corporation, Bangalore, India","Microprocessor Research, Intel Labs, Intel Corporation, Bangalore, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Research, Intel Laboratories, Intel Corporation, Bangalore, India","institution_ids":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]},{"raw_affiliation_string":"Microprocessor Research, Intel Labs, Intel Corporation, Bangalore, India","institution_ids":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100974612","display_name":"Shasi Kumar","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN","US"],"is_corresponding":false,"raw_author_name":"Shasi Kumar","raw_affiliation_strings":["Microprocessor Research, Intel Laboratories, Intel Corporation, Bangalore, India","Microprocessor Research, Intel Labs, Intel Corporation, Bangalore, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Research, Intel Laboratories, Intel Corporation, Bangalore, India","institution_ids":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]},{"raw_affiliation_string":"Microprocessor Research, Intel Labs, Intel Corporation, Bangalore, India","institution_ids":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081522570","display_name":"Vasantha Erraguntla","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN","US"],"is_corresponding":false,"raw_author_name":"Vasantha Erraguntla","raw_affiliation_strings":["Microprocessor Research, Intel Laboratories, Intel Corporation, Bangalore, India","Microprocessor Research, Intel Labs, Intel Corporation, Bangalore, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Research, Intel Laboratories, Intel Corporation, Bangalore, India","institution_ids":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]},{"raw_affiliation_string":"Microprocessor Research, Intel Labs, Intel Corporation, Bangalore, India","institution_ids":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081186735","display_name":"Yatin Hoskote","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yatin Hoskote","raw_affiliation_strings":["Microprocessor Research, Intel Laboratories, Intel Corporation, Hillsboro, OR, USA","Microprocessor Res., Intel Labs., Intel Corp., Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Research, Intel Laboratories, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Microprocessor Res., Intel Labs., Intel Corp., Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102778960","display_name":"Sriram R. Vangal","orcid":"https://orcid.org/0000-0003-1548-9876","observed_orcids":["https://orcid.org/0000-0003-1548-9876"]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sriram Vangal","raw_affiliation_strings":["Microprocessor Research, Intel Laboratories, Intel Corporation, Hillsboro, OR, USA","Microprocessor Res., Intel Labs., Intel Corp., Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Research, Intel Laboratories, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Microprocessor Res., Intel Labs., Intel Corp., Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108599907","display_name":"Gregory Ruhl","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Gregory Ruhl","raw_affiliation_strings":["Microprocessor Research, Intel Laboratories, Intel Corporation, Hillsboro, OR, USA","Microprocessor Res., Intel Labs., Intel Corp., Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Research, Intel Laboratories, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Microprocessor Res., Intel Labs., Intel Corp., Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054552830","display_name":"Partha Kundu","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Partha Kundu","raw_affiliation_strings":["Microprocessor Research, Intel Laboratories, Intel Corporation, Santa Clara, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Research, Intel Laboratories, Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112900267","display_name":"Nitin Borkar","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nitin Borkar","raw_affiliation_strings":["Microprocessor Research, Intel Laboratories, Intel Corporation, Hillsboro, OR, USA","Microprocessor Res., Intel Labs., Intel Corp., Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microprocessor Research, Intel Laboratories, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Microprocessor Res., Intel Labs., Intel Corp., Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.6237,"has_fulltext":false,"cited_by_count":22,"citation_normalized_percentile":{"value":0.91509115,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":88,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"79","last_page":"80"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/network-on-chip","display_name":"network-on-chip","score":0.9909999966621399},{"id":"https://openalex.org/keywords/2d-mesh-topology","display_name":"2D mesh topology","score":0.796999990940094},{"id":"https://openalex.org/keywords/dynamic-voltage-and-frequency-scaling","display_name":"dynamic voltage and frequency scaling","score":0.765999972820282},{"id":"https://openalex.org/keywords/router-design","display_name":"router design","score":0.5479999780654907},{"id":"https://openalex.org/keywords/virtual-channel-routing","display_name":"virtual channel routing","score":0.5820000171661377},{"id":"https://openalex.org/keywords/energy-efficiency","display_name":"energy efficiency","score":0.7160000205039978},{"id":"https://openalex.org/keywords/45-nm-cmos","display_name":"45 nm CMOS","score":0.8209999799728394},{"id":"https://openalex.org/keywords/bisection-bandwidth","display_name":"bisection bandwidth","score":0.8199999928474426}],"concepts":[{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.7902308702468872},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5496866703033447},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4331645369529724},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3923875391483307},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.3757737874984741},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.3479359745979309},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.32961446046829224},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.24754610657691956},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.23964622616767883},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20134583115577698}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsic.2010.5560277","doi":"https://doi.org/10.1109/vlsic.2010.5560277","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsic.2010.5560277","pdf_url":null,"source":{"id":"https://openalex.org/S4393918263","display_name":"Symposium on VLSI Circuits","issn_l":"2166-9600","issn":["2166-9600"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":["jufo-1"],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Symposium on VLSI Circuits","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.8970999717712402}],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1974420955","https://openalex.org/W2096383657","https://openalex.org/W2104674486","https://openalex.org/W2108085346"],"related_works":["https://openalex.org/W2163947402","https://openalex.org/W2147521557","https://openalex.org/W2119117967","https://openalex.org/W2372286077","https://openalex.org/W2965444073","https://openalex.org/W2035699920","https://openalex.org/W7100558985","https://openalex.org/W4321066993","https://openalex.org/W2083722722","https://openalex.org/W2248680862"],"abstract_inverted_index":{"A":[0],"packet-switched":[1],"6\u00d74":[2],"2D":[3],"mesh":[4],"network-on-chip":[5],"(NoC)":[6],"on":[7],"a":[8,57],"dedicated":[9],"voltage":[10],"and":[11,21,27,52,56],"frequency":[12],"island":[13],"(VFI)":[14],"provides":[15],"2":[16,72],"Tb/s":[17,33],"of":[18],"bisection":[19],"bandwidth,":[20],"interconnects":[22],"48":[23],"Pentium\u2122class":[24],"IA-32":[25],"cores":[26],"4":[28],"DDR3":[29],"channels.":[30],"The":[31,64],"1.28":[32],"router":[34],"with":[35],"16":[36],"B,":[37],"5.4":[38],"mm":[39],"links":[40],"achieves":[41],"high":[42],"network":[43],"utilization":[44],"through":[45],"8":[46],"virtual":[47],"channels":[48],"(VC),":[49],"early-buffer":[50],"write":[51],"read,":[53],"route":[54],"pre-computation":[55],"1-cycle":[58],"wrapped":[59],"wavefront":[60],"allocator":[61],"(WWFA)":[62],"design.":[63],"640":[65],"K":[66],"transistor,":[67],"1.17":[68],"mm2router":[69],"operates":[70],"at":[71,74],"GHz":[73],"1.1":[75],"V":[76],"while":[77],"dissipating":[78],"550":[79],"mW.":[80],"Router":[81],"energy":[82],"efficiency":[83],"scales":[84],"up":[85],"to":[86],"7.2":[87],"Tb/s/W.":[88]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2016,"cited_by_count":5},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":7}],"updated_date":"2026-11-07T11:25:07.637180","created_date":"2016-06-24T00:00:00"}