{"id":"https://openalex.org/W2106738951","doi":"https://doi.org/10.1109/ijcnn.1992.226993","title":"Digital VLSI multiprocessor design for neurocomputers","display_name":"Digital VLSI multiprocessor design for neurocomputers","publication_year":2003,"publication_date":"2003-01-02","ids":{"openalex":"https://openalex.org/W2106738951","doi":"https://doi.org/10.1109/ijcnn.1992.226993","mag":"2106738951"},"language":"en","primary_location":{"id":"doi:10.1109/ijcnn.1992.226993","doi":"https://doi.org/10.1109/ijcnn.1992.226993","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ijcnn.1992.226993","pdf_url":null,"source":{"id":"https://openalex.org/S4363607707","display_name":"International Joint Conference on Neural Networks (IJCNN)","issn_l":"2161-4407","issn":["2161-4407"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":["jufo-1","norway-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"[Proceedings 1992] IJCNN International Joint Conference on Neural Networks","raw_type":"proceedings-article"},"parent_works":[],"lineage":["https://openalex.org/W2106738951"],"child_works_count":0,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"C.-F. Chang","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"C.-F. Chang","raw_affiliation_strings":["Department of Electrical Engineering, Center for Neural Engineering the Signal and Image Processing Institute, University of Southern California, Los Angeles, CA, USA","Dept. of Electr. Eng. Univ. of Southern California, Los Angeles, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Center for Neural Engineering the Signal and Image Processing Institute, University of Southern California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I1174212"]},{"raw_affiliation_string":"Dept. of Electr. Eng. Univ. of Southern California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I1174212"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5086274866","display_name":"B.J. Sheu","orcid":"https://orcid.org/0000-0002-4405-2350","observed_orcids":["https://orcid.org/0000-0002-4405-2350"]},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"B.J. Sheu","raw_affiliation_strings":["Department of Electrical Engineering, Center for Neural Engineering the Signal and Image Processing Institute, University of Southern California, Los Angeles, CA, USA","Dept. of Electr. Eng. Univ. of Southern California, Los Angeles, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Center for Neural Engineering the Signal and Image Processing Institute, University of Southern California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I1174212"]},{"raw_affiliation_string":"Dept. of Electr. Eng. Univ. of Southern California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I1174212"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1174212"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.0,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":88,"max":93},"biblio":{"volume":"2","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.2087000012397766,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.2087000012397766,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10320","display_name":"Neural Networks and Applications","score":0.14589999616146088,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.14499999582767487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/neurocomputers","display_name":"neurocomputers","score":0.8109999895095825},{"id":"https://openalex.org/keywords/back-propagation-neural-network","display_name":"BP neural network","score":0.906000018119812},{"id":"https://openalex.org/keywords/cmos-circuit-design","display_name":"CMOS circuit design","score":0.7620000243186951}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7377371788024902},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6884567737579346},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.6026251316070557},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5864104628562927},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.5811976790428162},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5758456587791443},{"id":"https://openalex.org/C203479927","wikidata":"https://www.wikidata.org/wiki/Q5165939","display_name":"Controller (irrigation)","level":2,"score":0.4687115550041199},{"id":"https://openalex.org/C106515295","wikidata":"https://www.wikidata.org/wiki/Q26806595","display_name":"Parallel processing","level":2,"score":0.44817012548446655},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.38802728056907654},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3805880546569824},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36934420466423035},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.16158205270767212},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13545337319374084},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08959585428237915},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C6557445","wikidata":"https://www.wikidata.org/wiki/Q173113","display_name":"Agronomy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ijcnn.1992.226993","doi":"https://doi.org/10.1109/ijcnn.1992.226993","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ijcnn.1992.226993","pdf_url":null,"source":{"id":"https://openalex.org/S4363607707","display_name":"International Joint Conference on Neural Networks (IJCNN)","issn_l":"2161-4407","issn":["2161-4407"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":["jufo-1","norway-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"[Proceedings 1992] IJCNN International Joint Conference on Neural Networks","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320307102","display_name":"Intel Corporation","ror":"https://ror.org/01ek73717"},{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1546843038","https://openalex.org/W1554885925","https://openalex.org/W1637630365","https://openalex.org/W1981071268","https://openalex.org/W1999497791","https://openalex.org/W2051189822","https://openalex.org/W2107198528","https://openalex.org/W2135955108","https://openalex.org/W2153234467","https://openalex.org/W2766736793","https://openalex.org/W4254977194","https://openalex.org/W4300402905","https://openalex.org/W4302458519"],"related_works":["https://openalex.org/W1527597880","https://openalex.org/W2143714317","https://openalex.org/W2096192980","https://openalex.org/W2111680036","https://openalex.org/W3120359732","https://openalex.org/W2141332912","https://openalex.org/W184465766","https://openalex.org/W1515714068","https://openalex.org/W2154421062","https://openalex.org/W1569253753"],"abstract_inverted_index":{"The":[0,13],"architecture":[1],"and":[2,47],"circuit":[3,67],"design":[4,64],"of":[5,44,65,86],"digital":[6],"processors":[7],"for":[8,18],"general-purpose":[9],"neurocomputing":[10],"are":[11,61],"presented.":[12],"processing":[14,41,58,75],"element":[15,59],"is":[16,69],"suitable":[17],"a":[19,81],"tightly":[20],"coupled":[21],"multiprocessor":[22],"chip":[23,83],"connected":[24],"in":[25,50,80],"one-dimensional":[26],"ring":[27],"or":[28],"two-dimensional":[29],"mesh":[30],"fashion.":[31],"An":[32],"off-chip":[33],"microprogrammed":[34],"array":[35],"controller":[36],"broadcasts":[37],"instructions":[38],"to":[39,93],"all":[40],"elements.":[42],"Mappings":[43],"the":[45,51,56,66],"feedforward":[46],"feedback":[48],"operations":[49,97],"backpropagation":[52],"neural":[53],"network":[54],"into":[55],"mesh-connected":[57],"matrix":[60],"described.":[62,71],"Detailed":[63],"blocks":[68],"also":[70],"More":[72],"than":[73],"128":[74],"elements":[76],"can":[77],"be":[78],"implemented":[79],"super":[82],"by":[84],"use":[85],"advanced":[87],"0.5-":[88],"mu":[89],"m":[90],"CMOS":[91],"technology":[92],"achieve":[94],"2.56":[95],"billion":[96],"per":[98],"second.>":[99]},"counts_by_year":[{"year":2020,"cited_by_count":1}],"updated_date":"2026-11-14T11:04:58.165337","created_date":"2016-06-24T00:00:00"}
