{"id":"https://openalex.org/W2106550461","doi":"https://doi.org/10.1109/isscc.2004.1332641","title":"Ultra-low voltage circuits and processor in 180nm to 90nm technologies with a swapped-body biasing technique","display_name":"Ultra-low voltage circuits and processor in 180nm to 90nm technologies with a swapped-body biasing technique","publication_year":2004,"publication_date":"2004-09-28","ids":{"openalex":"https://openalex.org/W2106550461","doi":"https://doi.org/10.1109/isscc.2004.1332641","mag":"2106550461"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.2004.1332641","doi":"https://doi.org/10.1109/isscc.2004.1332641","is_oa":true,"landing_page_url":"https://doi.org/10.1109/isscc.2004.1332641","pdf_url":null,"source":{"id":"https://openalex.org/S4210210374","display_name":"Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference","issn_l":"0193-6530","issn":["0193-6530","2376-8606"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","norway-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://doi.org/10.1109/isscc.2004.1332641","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5091080461","display_name":"S. Narendra","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Narendra","raw_affiliation_strings":["Intel, Hillsboro, OR","Intel Corporation, , Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067753561","display_name":"James W. Tschanz","orcid":"https://orcid.org/0000-0003-0317-4332","observed_orcids":["https://orcid.org/0000-0003-0317-4332"]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Tschanz","raw_affiliation_strings":["Intel, Hillsboro, OR","Intel Corporation, , Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091333814","display_name":"J. Hofsheier","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Hofsheier","raw_affiliation_strings":["Intel, Hillsboro, OR","Intel Corporation, , Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051283749","display_name":"B.A. Bloechel","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"B. Bloechel","raw_affiliation_strings":["Intel, Hillsboro, OR","Intel Corporation, , Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102778960","display_name":"Sriram R. Vangal","orcid":"https://orcid.org/0000-0003-1548-9876","observed_orcids":["https://orcid.org/0000-0003-1548-9876"]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Vangal","raw_affiliation_strings":["Intel, Hillsboro, OR","Intel Corporation, , Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081186735","display_name":"Yatin Hoskote","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Y. Hoskote","raw_affiliation_strings":["Intel, Hillsboro, OR","Intel Corporation, , Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101461407","display_name":"Sai Chun Tang","orcid":"https://orcid.org/0000-0001-7659-0981","observed_orcids":["https://orcid.org/0000-0001-7659-0981"]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Tang","raw_affiliation_strings":["Intel, Hillsboro, OR","Intel Corporation, , Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006467285","display_name":"Dinesh Somasekhar","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D. Somasekhar","raw_affiliation_strings":["Intel, Hillsboro, OR","Intel Corporation, , Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103040522","display_name":"A. Keshavarzi","orcid":"https://orcid.org/0000-0001-6938-1161","observed_orcids":["https://orcid.org/0000-0001-6938-1161"]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Keshavarzi","raw_affiliation_strings":["Intel, Hillsboro, OR","Intel Corporation, , Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081522570","display_name":"Vasantha Erraguntla","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"V. Erraguntla","raw_affiliation_strings":["Intel, Hillsboro, OR","Intel Corporation, , Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060530263","display_name":"G. E. Dermer","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"G. Dermer","raw_affiliation_strings":["Intel, Hillsboro, OR","Intel Corporation, , Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112900267","display_name":"Nitin Borkar","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"N. Borkar","raw_affiliation_strings":["Intel, Hillsboro, OR","Intel Corporation, , Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112875487","display_name":"Shekhar Y. Borkar","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Borkar","raw_affiliation_strings":["Intel, Hillsboro, OR","Intel Corporation, , Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5076642880","display_name":"Vivek K. De","orcid":"https://orcid.org/0000-0001-5207-1079","observed_orcids":["https://orcid.org/0000-0001-5207-1079"]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"V. De","raw_affiliation_strings":["Intel, Hillsboro, OR","Intel Corporation, , Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":9.1344,"has_fulltext":false,"cited_by_count":85,"citation_normalized_percentile":{"value":0.98786909,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":88,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"156","last_page":"518"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9839000105857849,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9839000105857849,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.011099999770522118,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.002899999963119626,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/ultra-low-voltage-circuits","display_name":"ultra-low-voltage circuits","score":0.8769999742507935},{"id":"https://openalex.org/keywords/substrate-bias","display_name":"substrate bias","score":0.765999972820282},{"id":"https://openalex.org/keywords/cmos-scaling","display_name":"CMOS scaling","score":0.5899999737739563},{"id":"https://openalex.org/keywords/0-18-mum-cmos","display_name":"0.18 \u03bcm CMOS","score":0.8080000281333923},{"id":"https://openalex.org/keywords/90-nm-cmos","display_name":"90 nm CMOS","score":1.0},{"id":"https://openalex.org/keywords/frequency-scaling","display_name":"frequency scaling","score":0.6669999957084656}],"concepts":[{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.878225564956665},{"id":"https://openalex.org/C20254490","wikidata":"https://www.wikidata.org/wiki/Q719550","display_name":"Biasing","level":3,"score":0.8753176927566528},{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.8176767230033875},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7424196600914001},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5408973693847656},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.5305963754653931},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.4672683775424957},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4353828728199005},{"id":"https://openalex.org/C128624480","wikidata":"https://www.wikidata.org/wiki/Q1504817","display_name":"Low voltage","level":3,"score":0.4351629912853241},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4243814945220947},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.40359166264533997},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.3864757716655731},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.35969290137290955},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24050694704055786},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.15451833605766296}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.2004.1332641","doi":"https://doi.org/10.1109/isscc.2004.1332641","is_oa":true,"landing_page_url":"https://doi.org/10.1109/isscc.2004.1332641","pdf_url":null,"source":{"id":"https://openalex.org/S4210210374","display_name":"Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference","issn_l":"0193-6530","issn":["0193-6530","2376-8606"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","norway-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1109/isscc.2004.1332641","doi":"https://doi.org/10.1109/isscc.2004.1332641","is_oa":true,"landing_page_url":"https://doi.org/10.1109/isscc.2004.1332641","pdf_url":null,"source":{"id":"https://openalex.org/S4210210374","display_name":"Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference","issn_l":"0193-6530","issn":["0193-6530","2376-8606"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","norway-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","raw_type":"proceedings-article"},"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2033110462","https://openalex.org/W2113774867","https://openalex.org/W2150526221","https://openalex.org/W2166677938","https://openalex.org/W6684765163"],"related_works":["https://openalex.org/W2613710223","https://openalex.org/W2048420745","https://openalex.org/W2014293693","https://openalex.org/W2908066329","https://openalex.org/W2102005192","https://openalex.org/W2470167512","https://openalex.org/W2560892427","https://openalex.org/W2124914815","https://openalex.org/W2276543315","https://openalex.org/W4238314219"],"abstract_inverted_index":{"A":[0],"low-voltage":[1],"swapped-body":[2],"biasing":[3],"technique":[4],"where":[5],"PMOS":[6],"bodies":[7,14],"are":[8],"connected":[9],"to":[10,15,33,43,49],"ground":[11],"and":[12,30],"NMOS":[13],"Vcc":[16,29,35],"is":[17],"evaluated.":[18],"Available":[19],"measurements":[20],"show":[21],"more":[22],"than":[23],"2.6x":[24],"frequency":[25,41],"improvement":[26],"at":[27],"0.5V":[28],"the":[31,39],"ability":[32],"reduce":[34],"by":[36],"0.2V":[37],"for":[38],"same":[40],"compared":[42],"no":[44],"body":[45],"bias":[46],"in":[47],"180":[48],"90nm":[50],"CMOS":[51],"technologies.":[52]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":6},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":5}],"updated_date":"2026-11-04T10:54:05.112534","created_date":"2016-06-24T00:00:00"}