{"id":"https://openalex.org/W2104696146","doi":"https://doi.org/10.1109/icm.1998.825560","title":"FPGA implementation using Renoir tools: application for bit timing logic (BTL) synthesis of controller area network with 100% free error","display_name":"FPGA implementation using Renoir tools: application for bit timing logic (BTL) synthesis of controller area network with 100% free error","publication_year":2002,"publication_date":"2002-11-27","ids":{"openalex":"https://openalex.org/W2104696146","doi":"https://doi.org/10.1109/icm.1998.825560","mag":"2104696146"},"language":"en","primary_location":{"id":"doi:10.1109/icm.1998.825560","doi":"https://doi.org/10.1109/icm.1998.825560","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icm.1998.825560","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075808611","display_name":"Kamel Abouda","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I4396570533","display_name":"Universit\u00e9 Bordeaux-I","ror":"https://ror.org/001anga17","country_code":"FR","type":"education","lineage":["https://openalex.org/I15057530","https://openalex.org/I4396570533"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"K. Abouda","raw_affiliation_strings":["Laboratoire d'Erude de I IntUMR-CNRS 5818 Universit\u00e9 Bordeaux Igration des Coinposanls et Sysbmes Electronique, UMR-CNRS 5818 Universit\u00e9 Bordeaux I, Talence, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Laboratoire d'Erude de I IntUMR-CNRS 5818 Universit\u00e9 Bordeaux Igration des Coinposanls et Sysbmes Electronique, UMR-CNRS 5818 Universit\u00e9 Bordeaux I, Talence, France","institution_ids":["https://openalex.org/I1294671590","https://openalex.org/I4396570533"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077188857","display_name":"J. Ducaud","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I4396570533","display_name":"Universit\u00e9 Bordeaux-I","ror":"https://ror.org/001anga17","country_code":"FR","type":"education","lineage":["https://openalex.org/I15057530","https://openalex.org/I4396570533"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"J. Ducaud","raw_affiliation_strings":["Laboratoire d'Erude de I IntUMR-CNRS 5818 Universit\u00e9 Bordeaux Igration des Coinposanls et Sysbmes Electronique, UMR-CNRS 5818 Universit\u00e9 Bordeaux I, Talence, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Laboratoire d'Erude de I IntUMR-CNRS 5818 Universit\u00e9 Bordeaux Igration des Coinposanls et Sysbmes Electronique, UMR-CNRS 5818 Universit\u00e9 Bordeaux I, Talence, France","institution_ids":["https://openalex.org/I1294671590","https://openalex.org/I4396570533"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027529759","display_name":"H. Henry","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I4396570533","display_name":"Universit\u00e9 Bordeaux-I","ror":"https://ror.org/001anga17","country_code":"FR","type":"education","lineage":["https://openalex.org/I15057530","https://openalex.org/I4396570533"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"H. Henry","raw_affiliation_strings":["Laboratoire d'Erude de I IntUMR-CNRS 5818 Universit\u00e9 Bordeaux Igration des Coinposanls et Sysbmes Electronique, UMR-CNRS 5818 Universit\u00e9 Bordeaux I, Talence, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Laboratoire d'Erude de I IntUMR-CNRS 5818 Universit\u00e9 Bordeaux Igration des Coinposanls et Sysbmes Electronique, UMR-CNRS 5818 Universit\u00e9 Bordeaux I, Talence, France","institution_ids":["https://openalex.org/I1294671590","https://openalex.org/I4396570533"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5023868257","display_name":"Jean-Louis Aucouturier","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I4396570533","display_name":"Universit\u00e9 Bordeaux-I","ror":"https://ror.org/001anga17","country_code":"FR","type":"education","lineage":["https://openalex.org/I15057530","https://openalex.org/I4396570533"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"J.L. Aucouturier","raw_affiliation_strings":["Laboratoire d'Erude de I IntUMR-CNRS 5818 Universit\u00e9 Bordeaux Igration des Coinposanls et Sysbmes Electronique, UMR-CNRS 5818 Universit\u00e9 Bordeaux I, Talence, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Laboratoire d'Erude de I IntUMR-CNRS 5818 Universit\u00e9 Bordeaux Igration des Coinposanls et Sysbmes Electronique, UMR-CNRS 5818 Universit\u00e9 Bordeaux I, Talence, France","institution_ids":["https://openalex.org/I1294671590","https://openalex.org/I4396570533"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3754,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.52789853,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"2 3","issue":null,"first_page":"29","last_page":"32"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":0.9843999743461609,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":0.9843999743461609,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.010200000368058681,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.004399999976158142,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/can-bus","display_name":"CAN bus","score":0.8309999704360962},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.5609999895095825},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"logic synthesis","score":0.6570000052452087},{"id":"https://openalex.org/keywords/fpga-implementation","display_name":"FPGA implementation","score":0.7770000100135803},{"id":"https://openalex.org/keywords/graphic-design-software","display_name":"graphic design software","score":0.6209999918937683}],"concepts":[{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.9432754516601562},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7549921274185181},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.6678886413574219},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5703946352005005},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5147045254707336},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.45742806792259216},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.39655235409736633},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.38743114471435547},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.38306304812431335},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3695896863937378},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.36748507618904114},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3223128616809845},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.22282612323760986}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icm.1998.825560","doi":"https://doi.org/10.1109/icm.1998.825560","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icm.1998.825560","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2940848692","https://openalex.org/W79816902","https://openalex.org/W2183286342","https://openalex.org/W2280531038","https://openalex.org/W2107935966","https://openalex.org/W1602372871","https://openalex.org/W3082660278","https://openalex.org/W2086723865","https://openalex.org/W7033608633","https://openalex.org/W4400601618"],"abstract_inverted_index":{"Logic":[0],"synthesis":[1],"using":[2],"VHDL":[3,19,33,43,51],"simplifies":[4],"considerably":[5],"logic":[6,72],"circuit":[7],"design.":[8],"However,":[9],"when":[10],"the":[11,32,42,58],"application":[12,63],"requires":[13],"a":[14,69],"few":[15],"thousand":[16],"lines":[17],"of":[18,57,73],"code,":[20],"it":[21,36],"is":[22,37,81],"very":[23],"beneficial":[24],"to":[25,40],"use":[26],"graphic":[27],"software":[28],"that":[29],"can":[30],"produce":[31],"code.":[34],"But,":[35],"always":[38],"necessary":[39],"master":[41],"language.":[44],"In":[45],"this":[46],"paper":[47],"we":[48],"have":[49],"studied":[50],"generated":[52],"with":[53,87],"three":[54],"basic":[55],"processes":[56],"Renoir":[59],"state":[60],"machine.":[61],"An":[62],"for":[64],"designing,":[65],"synthesizing":[66],"and":[67],"implementing":[68],"bit":[70],"timing":[71],"an":[74],"ISO":[75],"normalized":[76],"controller":[77],"area":[78],"network":[79],"(CAN)":[80],"given.":[82],"It":[83],"has":[84],"been":[85],"tested":[86],"100%":[88],"free":[89],"error.":[90]},"counts_by_year":[],"updated_date":"2026-10-27T15:51:10.671819","created_date":"2016-06-24T00:00:00"}