{"id":"https://openalex.org/W2099216271","doi":"https://doi.org/10.1109/euc.2008.116","title":"Single Instruction Dual-Execution Model Processor Architecture","display_name":"Single Instruction Dual-Execution Model Processor Architecture","publication_year":2008,"publication_date":"2008-12-01","ids":{"openalex":"https://openalex.org/W2099216271","doi":"https://doi.org/10.1109/euc.2008.116","mag":"2099216271"},"language":"en","primary_location":{"id":"doi:10.1109/euc.2008.116","doi":"https://doi.org/10.1109/euc.2008.116","is_oa":false,"landing_page_url":"https://doi.org/10.1109/euc.2008.116","pdf_url":null,"source":{"id":"https://openalex.org/S7407087947","display_name":"IEEE International Conference on Computational Science and Engineering (CSE) and IEEE International Conference on Embedded and Ubiquitous Computing (EUC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5090780884","display_name":"Taichi Maekawa","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I141591182","display_name":"University of Aizu","ror":"https://ror.org/02pg0e883","country_code":"JP","type":"education","lineage":["https://openalex.org/I141591182"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Taichi Maekawa","raw_affiliation_strings":["School of Computer Science and Engineering, Adaptive System Laboratory, University of Aizu, Fukushima, Japan","Sch. of Comput. Sci. & Eng., Univ. of Aizu., Aizu-Wakamatsu"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer Science and Engineering, Adaptive System Laboratory, University of Aizu, Fukushima, Japan","institution_ids":["https://openalex.org/I141591182"]},{"raw_affiliation_string":"Sch. of Comput. Sci. & Eng., Univ. of Aizu., Aizu-Wakamatsu","institution_ids":["https://openalex.org/I141591182"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023707202","display_name":"Abderazek Ben Abdallah","orcid":"https://orcid.org/0000-0003-3432-0718","observed_orcids":["https://orcid.org/0000-0003-3432-0718"]},"institutions":[{"id":"https://openalex.org/I141591182","display_name":"University of Aizu","ror":"https://ror.org/02pg0e883","country_code":"JP","type":"education","lineage":["https://openalex.org/I141591182"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Ben A. Abderazek","raw_affiliation_strings":["School of Computer Science and Engineering, Adaptive System Laboratory, University of Aizu, Fukushima, Japan","Sch. of Comput. Sci. & Eng., Univ. of Aizu., Aizu-Wakamatsu"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer Science and Engineering, Adaptive System Laboratory, University of Aizu, Fukushima, Japan","institution_ids":["https://openalex.org/I141591182"]},{"raw_affiliation_string":"Sch. of Comput. Sci. & Eng., Univ. of Aizu., Aizu-Wakamatsu","institution_ids":["https://openalex.org/I141591182"]}]},{"author_position":"last","author":{"id":null,"display_name":"Kenichi Kuroda","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I141591182","display_name":"University of Aizu","ror":"https://ror.org/02pg0e883","country_code":"JP","type":"education","lineage":["https://openalex.org/I141591182"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kenichi Kuroda","raw_affiliation_strings":["School of Computer Science and Engineering, Adaptive System Laboratory, University of Aizu, Fukushima, Japan","Sch. of Comput. Sci. & Eng., Univ. of Aizu., Aizu-Wakamatsu"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer Science and Engineering, Adaptive System Laboratory, University of Aizu, Fukushima, Japan","institution_ids":["https://openalex.org/I141591182"]},{"raw_affiliation_string":"Sch. of Comput. Sci. & Eng., Univ. of Aizu., Aizu-Wakamatsu","institution_ids":["https://openalex.org/I141591182"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I141591182"],"apc_list":null,"apc_paid":null,"fwci":0.3919,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.52050058,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"30","last_page":"36"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.7318999767303467,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.7318999767303467,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.09520000219345093,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.0406000018119812,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/instruction-set-architecture","display_name":"instruction set architecture","score":0.7070000171661377},{"id":"https://openalex.org/keywords/dynamic-switching","display_name":"dynamic switching","score":0.42399999499320984},{"id":"https://openalex.org/keywords/single-core-processors","display_name":"single-core processors","score":0.5609999895095825},{"id":"https://openalex.org/keywords/processor-architecture","display_name":"processor architecture","score":0.5}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8487640619277954},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6407574415206909},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.6252275705337524},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5633256435394287},{"id":"https://openalex.org/C160403385","wikidata":"https://www.wikidata.org/wiki/Q220543","display_name":"Queue","level":2,"score":0.5217479467391968},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.5165718793869019},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5041803121566772},{"id":"https://openalex.org/C2780980858","wikidata":"https://www.wikidata.org/wiki/Q110022","display_name":"Dual (grammatical number)","level":2,"score":0.4882088005542755},{"id":"https://openalex.org/C9395851","wikidata":"https://www.wikidata.org/wiki/Q177929","display_name":"Stack (abstract data type)","level":2,"score":0.47084710001945496},{"id":"https://openalex.org/C2871975","wikidata":"https://www.wikidata.org/wiki/Q187466","display_name":"Processor register","level":4,"score":0.46979033946990967},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.45702242851257324},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4372919201850891},{"id":"https://openalex.org/C26951474","wikidata":"https://www.wikidata.org/wiki/Q629283","display_name":"Priority queue","level":3,"score":0.43578991293907166},{"id":"https://openalex.org/C1793878","wikidata":"https://www.wikidata.org/wiki/Q1153762","display_name":"Out-of-order execution","level":2,"score":0.4294125437736511},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.41511672735214233},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3130788207054138},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1437172293663025},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C124952713","wikidata":"https://www.wikidata.org/wiki/Q8242","display_name":"Literature","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.0},{"id":"https://openalex.org/C153247305","wikidata":"https://www.wikidata.org/wiki/Q835713","display_name":"Memory address","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/euc.2008.116","doi":"https://doi.org/10.1109/euc.2008.116","is_oa":false,"landing_page_url":"https://doi.org/10.1109/euc.2008.116","pdf_url":null,"source":{"id":"https://openalex.org/S7407087947","display_name":"IEEE International Conference on Computational Science and Engineering (CSE) and IEEE International Conference on Embedded and Ubiquitous Computing (EUC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"sustainable_development_goals_aurora":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1498172944","https://openalex.org/W1550350967","https://openalex.org/W1604047876","https://openalex.org/W2067165752","https://openalex.org/W2093194336","https://openalex.org/W2108577243","https://openalex.org/W2116094656","https://openalex.org/W2125133818","https://openalex.org/W2533853114","https://openalex.org/W2739649174","https://openalex.org/W6633164521"],"related_works":["https://openalex.org/W2182628976","https://openalex.org/W1497005489","https://openalex.org/W1498172944","https://openalex.org/W2000227992","https://openalex.org/W2100317219","https://openalex.org/W2341654444","https://openalex.org/W2184053448","https://openalex.org/W2125133818","https://openalex.org/W2383519240","https://openalex.org/W2050223659"],"abstract_inverted_index":{"We":[0,99],"present":[1,100],"in":[2,23,32,70,93,107],"this":[3],"paper":[4],"architecture":[5,15,50,102],"and":[6,19,35,51,83,104],"preliminary":[7],"evaluation":[8],"results":[9,106],"of":[10,111],"a":[11,24,41,63,108],"novel":[12],"dual-mode":[13],"processor":[14],"which":[16],"supports":[17],"queue":[18,46],"stack":[20],"computation":[21,47],"models":[22],"single":[25],"core.":[26],"The":[27,72],"core":[28],"is":[29,38,60],"highly":[30],"adaptable":[31],"both":[33],"functionality":[34],"configuration.":[36],"It":[37],"based":[39,88],"on":[40,76],"reduced":[42],"bit":[43],"produced":[44],"order":[45],"instruction":[48],"set":[49],"functions":[52],"into":[53],"Queue":[54,81],"or":[55],"Stack":[56,87],"execution":[57],"models.":[58],"This":[59],"achieved":[61],"via":[62],"so":[64],"called":[65],"dynamic":[66],"switching":[67],"mechanism":[68],"implemented":[69],"hardware.":[71],"current":[73],"design":[74,105],"focuses":[75],"the":[77,96,101],"ability":[78],"to":[79,85,95],"execute":[80],"programs":[82,89],"also":[84],"support":[86],"without":[90],"considerable":[91],"increase":[92],"hardware":[94],"base":[97],"architecture.":[98],"description":[103],"fair":[109],"amount":[110],"details.":[112]},"counts_by_year":[{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1}],"updated_date":"2026-10-29T09:56:32.521200","created_date":"2016-06-24T00:00:00"}