{"id":"https://openalex.org/W2099136913","doi":"https://doi.org/10.1109/eurmic.1994.390403","title":"High level synthesis based on formal methods","display_name":"High level synthesis based on formal methods","publication_year":2002,"publication_date":"2002-12-17","ids":{"openalex":"https://openalex.org/W2099136913","doi":"https://doi.org/10.1109/eurmic.1994.390403","mag":"2099136913"},"language":"en","primary_location":{"id":"doi:10.1109/eurmic.1994.390403","doi":"https://doi.org/10.1109/eurmic.1994.390403","is_oa":false,"landing_page_url":"https://doi.org/10.1109/eurmic.1994.390403","pdf_url":null,"source":{"id":"https://openalex.org/S4306523317","display_name":"EUROMICRO Conference","issn_l":"1089-6503","issn":["1089-6503","2376-9505"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":["norway-1"],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of Twentieth Euromicro Conference. System Architecture and Integration","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5066095640","display_name":"Werner Grass","orcid":"https://orcid.org/0000-0002-4388-5203","observed_orcids":["https://orcid.org/0000-0002-4388-5203"]},"institutions":[{"id":"https://openalex.org/I186354981","display_name":"University of Passau","ror":"https://ror.org/05ydjnb78","country_code":"DE","type":"education","lineage":["https://openalex.org/I186354981"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"W. Grass","raw_affiliation_strings":["Faculty for Mathematics and Computer Science, University of Passau, Passau, Germany","[Fac. for Math. & Comput. Sci., Passau Univ., Germany]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty for Mathematics and Computer Science, University of Passau, Passau, Germany","institution_ids":["https://openalex.org/I186354981"]},{"raw_affiliation_string":"[Fac. for Math. & Comput. Sci., Passau Univ., Germany]","institution_ids":["https://openalex.org/I186354981"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061910091","display_name":"Matthias Mutz","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I186354981","display_name":"University of Passau","ror":"https://ror.org/05ydjnb78","country_code":"DE","type":"education","lineage":["https://openalex.org/I186354981"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"M. Mutz","raw_affiliation_strings":["Faculty for Mathematics and Computer Science, University of Passau, Passau, Germany","[Fac. for Math. & Comput. Sci., Passau Univ., Germany]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty for Mathematics and Computer Science, University of Passau, Passau, Germany","institution_ids":["https://openalex.org/I186354981"]},{"raw_affiliation_string":"[Fac. for Math. & Comput. Sci., Passau Univ., Germany]","institution_ids":["https://openalex.org/I186354981"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5010367285","display_name":"Wolf-Dieter Tiedemann","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I186354981","display_name":"University of Passau","ror":"https://ror.org/05ydjnb78","country_code":"DE","type":"education","lineage":["https://openalex.org/I186354981"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"W.-D. Tiedemann","raw_affiliation_strings":["Faculty for Mathematics and Computer Science, University of Passau, Passau, Germany","[Fac. for Math. & Comput. Sci., Passau Univ., Germany]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty for Mathematics and Computer Science, University of Passau, Passau, Germany","institution_ids":["https://openalex.org/I186354981"]},{"raw_affiliation_string":"[Fac. for Math. & Comput. Sci., Passau Univ., Germany]","institution_ids":["https://openalex.org/I186354981"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I186354981"],"apc_list":null,"apc_paid":null,"fwci":1.2039,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.77938629,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"38","issue":null,"first_page":"83","last_page":"91"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":9.999999747378752e-05,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":0.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"high-level synthesis","score":0.9950000047683716},{"id":"https://openalex.org/keywords/formal-methods","display_name":"formal methods","score":0.8180000185966492},{"id":"https://openalex.org/keywords/formal-verification","display_name":"formal verification","score":0.8429999947547913},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"register transfer level","score":0.8619999885559082},{"id":"https://openalex.org/keywords/scheduling","display_name":"scheduling","score":0.3709999918937683},{"id":"https://openalex.org/keywords/hardware-synthesis","display_name":"hardware synthesis","score":0.5889999866485596},{"id":"https://openalex.org/keywords/design-correctness","display_name":"design correctness","score":0.43700000643730164},{"id":"https://openalex.org/keywords/timing-verification","display_name":"timing verification","score":0.6029999852180481}],"concepts":[{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.7972027063369751},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.7935190796852112},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7485682964324951},{"id":"https://openalex.org/C127705205","wikidata":"https://www.wikidata.org/wiki/Q5748245","display_name":"Heuristics","level":2,"score":0.7028529644012451},{"id":"https://openalex.org/C75606506","wikidata":"https://www.wikidata.org/wiki/Q1049183","display_name":"Formal methods","level":2,"score":0.7014079689979553},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.5871993899345398},{"id":"https://openalex.org/C116253237","wikidata":"https://www.wikidata.org/wiki/Q1437424","display_name":"Formal specification","level":2,"score":0.5069780349731445},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.49808692932128906},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.4628419578075409},{"id":"https://openalex.org/C14331664","wikidata":"https://www.wikidata.org/wiki/Q3417382","display_name":"Refinement","level":3,"score":0.45208775997161865},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.416363000869751},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.22336682677268982},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.21968963742256165},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.15122735500335693},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.13813841342926025},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08378446102142334}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/eurmic.1994.390403","doi":"https://doi.org/10.1109/eurmic.1994.390403","is_oa":false,"landing_page_url":"https://doi.org/10.1109/eurmic.1994.390403","pdf_url":null,"source":{"id":"https://openalex.org/S4306523317","display_name":"EUROMICRO Conference","issn_l":"1089-6503","issn":["1089-6503","2376-9505"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":["norway-1"],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of Twentieth Euromicro Conference. System Architecture and Integration","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1520573145","https://openalex.org/W1522888794","https://openalex.org/W1578460247","https://openalex.org/W1581108287","https://openalex.org/W1593445040","https://openalex.org/W2034962526","https://openalex.org/W2081108518","https://openalex.org/W2085887317","https://openalex.org/W2099621810","https://openalex.org/W2110101313","https://openalex.org/W2151103736","https://openalex.org/W2165093646","https://openalex.org/W2171717938","https://openalex.org/W2493328864","https://openalex.org/W4234855984","https://openalex.org/W4252729222","https://openalex.org/W6685396315"],"related_works":["https://openalex.org/W2999183100","https://openalex.org/W2125998542","https://openalex.org/W6927130621","https://openalex.org/W2509111798","https://openalex.org/W1026453271","https://openalex.org/W2184191074","https://openalex.org/W4393035435","https://openalex.org/W7098362403","https://openalex.org/W2093032919","https://openalex.org/W2169233369"],"abstract_inverted_index":{"High-level":[0],"synthesis,":[1],"the":[2,10,34,38,43,73,103,124],"task":[3],"of":[4,25,62,102,128],"automatically":[5],"transforming":[6],"behavioural":[7],"descriptions":[8],"at":[9],"algorithmic":[11],"level":[12,16,86],"into":[13],"register":[14],"transfer":[15],"structures,":[17],"is":[18,107,136],"conquered":[19],"today":[20],"almost":[21],"always":[22],"by":[23,139],"use":[24],"heuristics.":[26],"This":[27,57],"prevents":[28],"giving":[29],"a":[30,83],"guarantee":[31],"either":[32],"for":[33],"design":[35],"optimality":[36],"or":[37],"correctness,":[39],"although":[40],"these":[41],"are":[42,88],"most":[44],"essential":[45],"criteria.":[46],"By":[47],"applying":[48],"formal":[49,69,74],"methods,":[50,70],"both":[51],"issues":[52],"can":[53],"be":[54],"formally":[55,125],"proven.":[56],"paper":[58],"presents":[59],"3":[60],"aspects":[61],"HLS,":[63],"that":[64,76,106,135],"have":[65],"been":[66],"solved":[67],"using":[68],"namely":[71],"(1)":[72],"verification":[75],"those":[77],"hardware":[78],"modules":[79],"allocated":[80],"to":[81,94,110],"realize":[82],"particular":[84],"RT":[85],"operation":[87],"actually":[89],"doing":[90],"so":[91],"with":[92,112],"respect":[93],"functionality":[95],"and":[96,122],"timing,":[97],"(2)":[98],"an":[99,131],"exact":[100],"solution":[101],"scheduling":[104],"problem":[105],"yet":[108],"able":[109],"cope":[111],"more":[113],"practical":[114],"constraints":[115],"than":[116],"any":[117],"heuristical":[118],"procedure":[119],"currently":[120],"known":[121],"(3)":[123],"based":[126],"synthesis":[127],"communication-dominated":[129],"hardware,":[130],"important":[132],"application":[133],"area":[134],"largely":[137],"unnoticed":[138],"today's":[140],"HLS":[141],"systems.>":[142]},"counts_by_year":[],"updated_date":"2026-11-04T10:54:05.112534","created_date":"2016-06-24T00:00:00"}
