{"id":"https://openalex.org/W2098515451","doi":"https://doi.org/10.5555/832284.835415","title":"Functional Verification of System on Chips-Practices, Issues and Challenges","display_name":"Functional Verification of System on Chips-Practices, Issues and Challenges","publication_year":2002,"publication_date":"2002-01-07","ids":{"openalex":"https://openalex.org/W2098515451","doi":"https://doi.org/10.5555/832284.835415","mag":"2098515451"},"language":"en","primary_location":{"id":"mag:2098515451","doi":"https://doi.org/10.5555/832284.835415","is_oa":false,"landing_page_url":"https://dl.acm.org/doi/10.5555/832284.835415","pdf_url":null,"source":{"id":"https://openalex.org/S4363608791","display_name":"Asia and South Pacific Design Automation Conference (ASP-DAC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":"Asia and South Pacific Design Automation Conference","raw_type":null},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":[],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020532266","display_name":"Subir Kumar Roy","orcid":"https://orcid.org/0000-0002-3554-1312","observed_orcids":["https://orcid.org/0000-0002-3554-1312"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Subir Kumar Roy","raw_affiliation_strings":["Synplicity, Inc"],"raw_orcid":"https://orcid.org/0000-0002-3554-1312","affiliations":[{"raw_affiliation_string":"Synplicity, Inc","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081333705","display_name":"S. Ramesh","orcid":"https://orcid.org/0000-0003-1361-8224","observed_orcids":["https://orcid.org/0000-0003-1361-8224"]},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"S. Ramesh","raw_affiliation_strings":["Indian Institute of Technology, Bombay, India;"],"raw_orcid":"https://orcid.org/0000-0003-1361-8224","affiliations":[{"raw_affiliation_string":"Indian Institute of Technology, Bombay, India;","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089236765","display_name":"Supratik Chakraborty","orcid":"https://orcid.org/0000-0002-7527-7675","observed_orcids":["https://orcid.org/0000-0002-7527-7675"]},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Supratik Chakraborty","raw_affiliation_strings":["Indian Institute of Technology, Bombay, India;"],"raw_orcid":"https://orcid.org/0000-0002-7527-7675","affiliations":[{"raw_affiliation_string":"Indian Institute of Technology, Bombay, India;","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087997458","display_name":"Tsuneo Nakata","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I2252096349","display_name":"Fujitsu (Japan)","ror":"https://ror.org/038e2g226","country_code":"JP","type":"company","lineage":["https://openalex.org/I2252096349"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Tsuneo Nakata","raw_affiliation_strings":["Fujitsu Laboratories Limited (Japan)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fujitsu Laboratories Limited (Japan)","institution_ids":["https://openalex.org/I2252096349"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111449373","display_name":"Sreeranga P. Rajan","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4210094759","display_name":"Fujitsu (United States)","ror":"https://ror.org/0073whr05","country_code":"US","type":"company","lineage":["https://openalex.org/I2252096349","https://openalex.org/I4210094759"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sreeranga P. Rajan","raw_affiliation_strings":["Fujitsu Labs. of America#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fujitsu Labs. of America#TAB#","institution_ids":["https://openalex.org/I4210094759"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.4025,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.50929253,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"11","last_page":"13"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9404000043869019,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9404000043869019,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.02710000053048134,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.019300000742077827,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/system-on-chip-verification","display_name":"system-on-chip verification","score":0.859000027179718},{"id":"https://openalex.org/keywords/functional-verification","display_name":"functional verification","score":0.9660000205039978},{"id":"https://openalex.org/keywords/ip-core","display_name":"IP core","score":0.7519999742507935},{"id":"https://openalex.org/keywords/compositional-verification","display_name":"compositional verification","score":0.9789999723434448},{"id":"https://openalex.org/keywords/formal-verification","display_name":"formal verification","score":0.8550000190734863},{"id":"https://openalex.org/keywords/semi-formal-verification","display_name":"semi-formal verification","score":0.9879999756813049},{"id":"https://openalex.org/keywords/emulation","display_name":"emulation","score":0.949999988079071},{"id":"https://openalex.org/keywords/formal-specification-languages","display_name":"formal specification languages","score":0.6690000295639038},{"id":"https://openalex.org/keywords/verification-cost","display_name":"verification costs","score":0.4860000014305115},{"id":"https://openalex.org/keywords/design-specifications","display_name":"design specifications","score":0.414000004529953},{"id":"https://openalex.org/keywords/verification-tools","display_name":"verification tools","score":0.4880000054836273},{"id":"https://openalex.org/keywords/hdl-cholesterol","display_name":"HDL cholesterol","score":0.36899998784065247}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7444713115692139},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.6985080242156982},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.6719174385070801},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.6219358444213867},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.529299259185791},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4634750783443451},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4528466463088989},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.4503260850906372},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.44853124022483826},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.44475269317626953},{"id":"https://openalex.org/C3406870","wikidata":"https://www.wikidata.org/wiki/Q6044160","display_name":"Intelligent verification","level":5,"score":0.4359716475009918},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4116842746734619},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.3854496479034424},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3813410699367523},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.36905837059020996},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.21896687150001526},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.1948544979095459},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17013147473335266},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1576901078224182},{"id":"https://openalex.org/C149091818","wikidata":"https://www.wikidata.org/wiki/Q2429814","display_name":"Software system","level":3,"score":0.1267167627811432},{"id":"https://openalex.org/C186846655","wikidata":"https://www.wikidata.org/wiki/Q3398377","display_name":"Software construction","level":4,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"mag:2098515451","doi":"https://doi.org/10.5555/832284.835415","is_oa":false,"landing_page_url":"https://dl.acm.org/doi/10.5555/832284.835415","pdf_url":null,"source":{"id":"https://openalex.org/S4363608791","display_name":"Asia and South Pacific Design Automation Conference (ASP-DAC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":"Asia and South Pacific Design Automation Conference","raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2183231635","https://openalex.org/W1645543439","https://openalex.org/W1490819086","https://openalex.org/W2373681493","https://openalex.org/W4250988410","https://openalex.org/W2168518353","https://openalex.org/W2354050233","https://openalex.org/W2077462114","https://openalex.org/W2613489159","https://openalex.org/W1550641714"],"abstract_inverted_index":{"System":[0],"on":[1,147,153,280,381,396,404],"Chip":[2],"(SoC)":[3],"designs":[4,258],"inherit":[5],"all":[6],"the":[7,53,60,71,109,118,124,166,175,184,187,202,213,223,251,271,291,312,344,347,350,373,382,385,388,419,433,438,445,452],"well":[8,42],"known":[9,43],"verification":[10,45,92,149,204,220,226,263,412,421,430],"and":[11,68,113,131,138,197,219,225,240,273,326,400,410,437],"validation":[12],"difficulties":[13],"associated":[14],"with":[15,183],"complex":[16,87],"ASIC":[17],"designs,":[18],"besides":[19],"adding":[20],"their":[21],"own":[22],"set":[23],"of":[24,52,66,136,150,165,172,174,186,246,289,314,319,324,335,337,339,349,384,390,427,440],"newer":[25],"problems.":[26],"These":[27],"arise":[28],"because":[29],"SoCs":[30,151,208],"are":[31,206,299,353],"primarily":[32],"implemented":[33],"by":[34,190,447],"re-using":[35],"Intellectual":[36],"Property":[37],"(IP)":[38],"cores.":[39],"It":[40,75,393],"is":[41,76,93,121,232,255,376],"that":[44,346,413],"today":[46],"constitutes":[47],"about":[48],"70%":[49],"to":[50,78,169,181,211,215,228,235,253,266,286,302,330,378,417],"80%":[51],"total":[54],"design":[55,73,89,130,188,193,195,198,218,224,238],"effort,":[56],"thereby,":[57],"making":[58],"it":[59],"most":[61],"expensive":[62],"component":[63],"in":[64,70,108,128,161,343,354,357,387],"terms":[65],"cost":[67],"time,":[69],"entire":[72],"flow.":[74],"expected":[77],"get":[79],"even":[80],"worse":[81],"for":[82,250,372,455],"SoC":[83,88,315,420],"designs.":[84],"In":[85],"a":[86,233,425],"flow":[90],"functional":[91,99,148,262,316,391],"very":[94],"important;":[95],"any":[96,298],"behavioral":[97],"or":[98,294,366],"bug":[100],"escaping":[101],"this":[102],"phase":[103],"will":[104,114,264,394],"not":[105],"be":[106,267,303,361,415],"detected":[107],"subsequent":[110],"implementation":[111,241],"phases":[112],"surface":[115],"only":[116],"after":[117],"first":[119],"silicon":[120,132],"integrated":[122],"into":[123],"target":[125],"system,":[126],"resulting":[127],"costly":[129],"iterations.":[133],"A":[134],"number":[135,426],"academic":[137],"industrial":[139],"research":[140,146],"laboratories":[141],"have":[142,180,209,265,301],"been":[143,159],"carrying":[144],"out":[145,217,269],"based":[152,279,403],"different":[154],"approaches.":[155],"Partial":[156],"success":[157,336],"has":[158],"achieved":[160],"deploying":[162],"them.":[163],"Many":[164],"issues":[167],"relate":[168],"intrinsic":[170],"limitations":[171],"some":[173,322,338,358],"approaches":[176,278,285,402],"taken;":[177],"while":[178],"others":[179],"do":[182],"quality":[185],"information,":[189],"way":[191],"of,":[192],"descriptions,":[194],"documentations":[196],"specifications,":[199],"from":[200],"which":[201,450],"overall":[203],"objectives":[205],"derived.":[207],"brought":[210],"focus":[212,395,454],"need":[214,234,252],"carry":[216],"concurrently.":[221],"For":[222,283],"task":[227],"proceed":[229],"concurrently":[230],"there":[231],"capture":[236],"formally,":[237],"information":[239,380],"details":[242],"at":[243],"various":[244,434],"levels":[245],"abstraction.":[247],"Another":[248],"reason":[249],"formalize":[254],"that,":[256],"as":[257],"become":[259],"more":[260],"complex,":[261],"carried":[268],"using":[270],"divide":[272,325],"conquer":[274,327],"approach.We":[275],"discuss":[276,424],"several":[277,308],"compositional":[281,331],"verification.":[282,317,332,392],"these":[284,320,340,441],"succeed,":[287],"specifications":[288,348],"either,":[290],"individual":[292,295],"modules,":[293],"IPs,":[296],"if":[297],"used,":[300],"stated":[304],"formally.":[305],"There":[306],"exist":[307],"commercial":[309],"offerings":[310],"addressing":[311],"area":[313,389],"Most":[318],"use":[321],"form":[323,451],"approach":[328],"related":[329],"The":[333],"basis":[334],"tools":[341],"lies":[342],"fact":[345],"IP":[351],"cores":[352],"essence":[355],"captured":[356],"executable":[359],"form,":[360],"they":[362],"formal":[363,408],"specification":[364],"languages,":[365],"commonly":[367],"used":[368,436],"HDLs":[369],"suitably":[370],"modified":[371],"purpose.This":[374],"tutorial":[375,446],"structured":[377],"provide":[379],"state":[383],"art":[386],"existing":[397],"methodologies,":[398],"tools,":[399],"practical":[401],"universal":[405],"simulation,":[406],"emulation,":[407],"verification,":[409],"semi-formal":[411],"can":[414],"employed":[416],"overcome":[418],"problem.":[422],"We":[423,443],"real":[428],"life":[429],"projects,":[431],"describing":[432],"techniques":[435],"effectiveness":[439],"techniques.":[442],"conclude":[444],"presenting":[448],"issues,":[449],"current":[453],"research.":[456]},"counts_by_year":[{"year":2017,"cited_by_count":1}],"updated_date":"2026-10-31T12:09:11.096373","created_date":"2016-06-24T00:00:00"}