{"id":"https://openalex.org/W2091305388","doi":"https://doi.org/10.1109/vts.2010.5469593","title":"A generic low power scan chain wrapper for designs using scan compression","display_name":"A generic low power scan chain wrapper for designs using scan compression","publication_year":2010,"publication_date":"2010-04-01","ids":{"openalex":"https://openalex.org/W2091305388","doi":"https://doi.org/10.1109/vts.2010.5469593","mag":"2091305388"},"language":"en","primary_location":{"id":"doi:10.1109/vts.2010.5469593","doi":"https://doi.org/10.1109/vts.2010.5469593","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2010.5469593","pdf_url":null,"source":{"id":"https://openalex.org/S4210180668","display_name":"IEEE VLSI Test Symposium (VTS)","issn_l":"1093-0167","issn":["1093-0167","2375-1053"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","jufo-1","norway-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 28th VLSI Test Symposium (VTS)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000932612","display_name":"Amit Sabne","orcid":"https://orcid.org/0000-0002-2179-0078","observed_orcids":["https://orcid.org/0000-0002-2179-0078"]},"institutions":[{"id":"https://openalex.org/I25547181","display_name":"Bharat Heavy Electricals (India)","ror":"https://ror.org/03ky3pc21","country_code":"IN","type":"company","lineage":["https://openalex.org/I25547181"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Amit Sabne","raw_affiliation_strings":["Bharat Heavy Electricals Limited, India","BHEL, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Bharat Heavy Electricals Limited, India","institution_ids":["https://openalex.org/I25547181"]},{"raw_affiliation_string":"BHEL, India","institution_ids":["https://openalex.org/I25547181"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Rajesh Tiwari","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4210109535","display_name":"Texas Instruments (India)","ror":"https://ror.org/01t305n31","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210109535","https://openalex.org/I74760111"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Rajesh Tiwari","raw_affiliation_strings":["Texas Instruments, Inc., India","[Texas Instruments, INDIA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas Instruments, Inc., India","institution_ids":["https://openalex.org/I4210109535"]},{"raw_affiliation_string":"[Texas Instruments, INDIA]","institution_ids":["https://openalex.org/I4210109535"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027352839","display_name":"Abhijeet Shrivastava","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4210109535","display_name":"Texas Instruments (India)","ror":"https://ror.org/01t305n31","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210109535","https://openalex.org/I74760111"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Abhijeet Shrivastava","raw_affiliation_strings":["Texas Instruments, Inc., India","[Texas Instruments, INDIA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas Instruments, Inc., India","institution_ids":["https://openalex.org/I4210109535"]},{"raw_affiliation_string":"[Texas Instruments, INDIA]","institution_ids":["https://openalex.org/I4210109535"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101754185","display_name":"Srivaths Ravi","orcid":"https://orcid.org/0000-0002-1306-2361","observed_orcids":["https://orcid.org/0000-0002-1306-2361"]},"institutions":[{"id":"https://openalex.org/I4210109535","display_name":"Texas Instruments (India)","ror":"https://ror.org/01t305n31","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210109535","https://openalex.org/I74760111"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Srivaths Ravi","raw_affiliation_strings":["Texas Instruments, Inc., India","[Texas Instruments, INDIA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas Instruments, Inc., India","institution_ids":["https://openalex.org/I4210109535"]},{"raw_affiliation_string":"[Texas Instruments, INDIA]","institution_ids":["https://openalex.org/I4210109535"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028519358","display_name":"Rubin Parekhji","orcid":"https://orcid.org/0009-0000-6625-2786","observed_orcids":["https://orcid.org/0009-0000-6625-2786"]},"institutions":[{"id":"https://openalex.org/I4210109535","display_name":"Texas Instruments (India)","ror":"https://ror.org/01t305n31","country_code":"IN","type":"company","lineage":["https://openalex.org/I4210109535","https://openalex.org/I74760111"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Rubin Parekhji","raw_affiliation_strings":["Texas Instruments, Inc., India","[Texas Instruments, INDIA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas Instruments, Inc., India","institution_ids":["https://openalex.org/I4210109535"]},{"raw_affiliation_string":"[Texas Instruments, INDIA]","institution_ids":["https://openalex.org/I4210109535"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.7973,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.85968631,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":88,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"135","last_page":"140"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.00039999998989515007,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.00019999999494757503,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scan-compression","display_name":"scan compression","score":0.7879999876022339},{"id":"https://openalex.org/keywords/test-power-reduction","display_name":"test power reduction","score":0.9520000219345093},{"id":"https://openalex.org/keywords/peak-current-reduction","display_name":"peak current reduction","score":0.722000002861023},{"id":"https://openalex.org/keywords/design-for-testability","display_name":"design for testability","score":0.6309999823570251},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"automatic test pattern generation","score":0.9049999713897705},{"id":"https://openalex.org/keywords/system-on-chip-testing","display_name":"system-on-chip testing","score":0.8500000238418579}],"concepts":[{"id":"https://openalex.org/C150012182","wikidata":"https://www.wikidata.org/wiki/Q225990","display_name":"Scan chain","level":3,"score":0.8968319892883301},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.7607999444007874},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.699726939201355},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5747185945510864},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5743556022644043},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5700223445892334},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5646370649337769},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.5372929573059082},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4822590947151184},{"id":"https://openalex.org/C16910744","wikidata":"https://www.wikidata.org/wiki/Q7705759","display_name":"Test data","level":2,"score":0.4673968255519867},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.46012234687805176},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.429187536239624},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.37745732069015503},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.30810099840164185},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.290310800075531},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.27367109060287476},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.2645912170410156},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.22958904504776},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1511310338973999},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08222901821136475},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vts.2010.5469593","doi":"https://doi.org/10.1109/vts.2010.5469593","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vts.2010.5469593","pdf_url":null,"source":{"id":"https://openalex.org/S4210180668","display_name":"IEEE VLSI Test Symposium (VTS)","issn_l":"1093-0167","issn":["1093-0167","2375-1053"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","jufo-1","norway-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 28th VLSI Test Symposium (VTS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5378999710083008,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1491971472","https://openalex.org/W1557977552","https://openalex.org/W1843801354","https://openalex.org/W1966348745","https://openalex.org/W2080510479","https://openalex.org/W2091472688","https://openalex.org/W2110232289","https://openalex.org/W2111569953","https://openalex.org/W2119691242","https://openalex.org/W2165516518","https://openalex.org/W2169734655"],"related_works":["https://openalex.org/W2144888713","https://openalex.org/W2542982212","https://openalex.org/W1973512152","https://openalex.org/W2182285458","https://openalex.org/W2031265978","https://openalex.org/W7098085561","https://openalex.org/W2120960137","https://openalex.org/W1997965829","https://openalex.org/W4404521288","https://openalex.org/W2151265211"],"abstract_inverted_index":{"Shrinking":[0],"power":[1,5,11,37,170,224],"budgets":[2],"in":[3,74,118,189,208],"low":[4],"system-on-chips":[6],"(SoCs)":[7],"have":[8,51,196],"elevated":[9],"test":[10,21,27,36,46,98,173],"consumption":[12],"as":[13],"a":[14,61,137,178,203,209],"major":[15],"consideration":[16],"for":[17,35,42,63,125,202,226],"chip":[18,89,228],"design":[19,56],"and":[20,31,79,115,221,233],"engineering":[22],"teams.":[23],"Many":[24],"traditional":[25],"automatic":[26],"pattern":[28],"generation":[29],"(ATPG)":[30],"design-for-test":[32],"(DFT)":[33],"techniques":[34],"reduction":[38],"are":[39,133],"either":[40],"effective":[41],"circuits":[43],"not":[44],"using":[45,152],"data":[47,218],"compression":[48,99,148],"hardware":[49],"or":[50,111,163],"implications":[52],"on":[53,83],"the":[54,75,97,122,127,185,231,236],"physical":[55,84],"cycle.":[57],"This":[58],"paper":[59],"describes":[60],"technique":[62],"reducing":[64],"peak":[65],"current":[66,129],"during":[67],"scan":[68,109,138,147,154,164,199,206],"based":[69],"testing":[70],"that":[71,103,141,180],"can":[72,142],"work":[73],"presence":[76],"of":[77,113,205,235],"compression,":[78],"impose":[80],"no":[81],"restrictions":[82],"design,":[85],"e.g.":[86],"related":[87],"to":[88,96,106,136,167,183,229],"clocking.":[90],"We":[91,176,215],"propose":[92],"low-design":[93],"effort":[94],"modifications":[95,132],"logic":[100],"(wrapper-like":[101],"changes)":[102],"enable":[104],"us":[105,182],"(a)":[107],"bypass":[108],"chains":[110,161,165,207],"groups":[112],"them":[114],"(b)":[116],"shift":[117],"constant":[119],"values":[120],"into":[121],"bypassed":[123,162],"flip-flops":[124],"lowering":[126],"instantaneous":[128],"drawn.":[130],"The":[131],"easily":[134],"localized":[135],"chain":[139,155,200],"wrapper":[140],"be":[143],"used":[144],"with":[145,172],"any":[146],"solution.":[149,191],"An":[150],"SoC":[151],"low-power":[153,198,213],"wrappers":[156,201],"provides":[157],"sufficient":[158],"configurability":[159,187],"(scan":[160],"included)":[166],"explore":[168],"different":[169],"reductions":[171],"cost":[174],"trade-offs.":[175],"describe":[177],"methodology":[179],"allows":[181],"manage":[184],"inherent":[186],"available":[188],"our":[190],"For":[192],"empirical":[193],"validation,":[194],"we":[195],"implemented":[197],"subset":[204],"recently":[210],"taped-out":[211],"65nm":[212],"SoC.":[214],"present":[216],"experimental":[217],"from":[219],"ATPG":[220],"initial":[222],"silicon":[223],"measurements":[225],"this":[227],"demonstrate":[230],"benefits":[232],"limitations":[234],"proposal.":[237]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":4}],"updated_date":"2026-10-27T15:51:10.671819","created_date":"2016-06-24T00:00:00"}
