{"id":"https://openalex.org/W2089930443","doi":"https://doi.org/10.1117/12.561122","title":"Analysis of an innovative user threshold programmable photoreceiver monolithically integrated in a multitechnology field programmable gate array (MT-FPGA)","display_name":"Analysis of an innovative user threshold programmable photoreceiver monolithically integrated in a multitechnology field programmable gate array (MT-FPGA)","publication_year":2004,"publication_date":"2004-10-22","ids":{"openalex":"https://openalex.org/W2089930443","doi":"https://doi.org/10.1117/12.561122","mag":"2089930443"},"language":"en","primary_location":{"id":"doi:10.1117/12.561122","doi":"https://doi.org/10.1117/12.561122","is_oa":false,"landing_page_url":"https://doi.org/10.1117/12.561122","pdf_url":null,"source":{"id":"https://openalex.org/S183492911","display_name":"Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE","issn_l":"0277-786X","issn":["0277-786X","1996-756X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","norway-1"],"host_organization":"https://openalex.org/P4310315543","host_organization_name":"SPIE","host_organization_lineage":["https://openalex.org/P4310315543"],"host_organization_lineage_names":["SPIE"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"SPIE Proceedings","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025053754","display_name":"Prosenjit Mal","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Prosenjit Mal","raw_affiliation_strings":["Intel Corp. (United States)","Intel Corporation, United States"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corp. (United States)","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, United States","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005909077","display_name":"Prashant R. Bhadri","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I63135867","display_name":"University of Cincinnati","ror":"https://ror.org/01e3m7079","country_code":"US","type":"education","lineage":["https://openalex.org/I63135867"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Prashant R. Bhadri","raw_affiliation_strings":["Univ. of Cincinnati (United States)","University of Cincinnati UNITED STATES"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Univ. of Cincinnati (United States)","institution_ids":["https://openalex.org/I63135867"]},{"raw_affiliation_string":"University of Cincinnati UNITED STATES","institution_ids":["https://openalex.org/I63135867"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5036344518","display_name":"Fred R. Beyette","orcid":"https://orcid.org/0000-0001-8704-7810","observed_orcids":["https://orcid.org/0000-0001-8704-7810"]},"institutions":[{"id":"https://openalex.org/I63135867","display_name":"University of Cincinnati","ror":"https://ror.org/01e3m7079","country_code":"US","type":"education","lineage":["https://openalex.org/I63135867"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Fred R. Beyette, Jr.","raw_affiliation_strings":["Univ. of Cincinnati (United States)","University of Cincinnati UNITED STATES"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Univ. of Cincinnati (United States)","institution_ids":["https://openalex.org/I63135867"]},{"raw_affiliation_string":"University of Cincinnati UNITED STATES","institution_ids":["https://openalex.org/I63135867"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.2093643,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"5557","issue":null,"first_page":"162","last_page":"162"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.4113999903202057,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.4113999903202057,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.13169999420642853,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10767","display_name":"Advanced Photonic Communication Systems","score":0.04899999871850014,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/photoreceiver","display_name":"photoreceiver","score":0.7820000052452087},{"id":"https://openalex.org/keywords/monolithic-integration","display_name":"monolithic integration","score":0.8679999709129333},{"id":"https://openalex.org/keywords/rapid-prototyping","display_name":"rapid prototyping","score":0.9309999942779541},{"id":"https://openalex.org/keywords/optical-information-processing","display_name":"optical information processing","score":0.7889999747276306},{"id":"https://openalex.org/keywords/analog-circuits","display_name":"analog circuits","score":0.4519999921321869}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.9025038480758667},{"id":"https://openalex.org/C2780149590","wikidata":"https://www.wikidata.org/wiki/Q7302742","display_name":"Reconfigurability","level":2,"score":0.8174594044685364},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7475533485412598},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.7287726402282715},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.660088062286377},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5577192306518555},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.5558058619499207},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.4818945527076721},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.4789729118347168},{"id":"https://openalex.org/C128315158","wikidata":"https://www.wikidata.org/wiki/Q1063858","display_name":"Complex programmable logic device","level":2,"score":0.47156092524528503},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.47113627195358276},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.44372496008872986},{"id":"https://openalex.org/C34370810","wikidata":"https://www.wikidata.org/wiki/Q3961319","display_name":"Simple programmable logic device","level":5,"score":0.43392854928970337},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.4325738549232483},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.43211042881011963},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.3608631193637848},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3149375319480896},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.24876472353935242},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.15752366185188293},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1395348608493805},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1117/12.561122","doi":"https://doi.org/10.1117/12.561122","is_oa":false,"landing_page_url":"https://doi.org/10.1117/12.561122","pdf_url":null,"source":{"id":"https://openalex.org/S183492911","display_name":"Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE","issn_l":"0277-786X","issn":["0277-786X","1996-756X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","norway-1"],"host_organization":"https://openalex.org/P4310315543","host_organization_name":"SPIE","host_organization_lineage":["https://openalex.org/P4310315543"],"host_organization_lineage_names":["SPIE"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"SPIE Proceedings","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7207000255584717,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2064975652","https://openalex.org/W1998757532","https://openalex.org/W2113897348","https://openalex.org/W1493349243","https://openalex.org/W2013040176","https://openalex.org/W1968951880","https://openalex.org/W2025007319","https://openalex.org/W2606969474","https://openalex.org/W7097737764","https://openalex.org/W2144557988"],"abstract_inverted_index":{"In":[0,18,146],"the":[1,12,15,21,41,48,60,90,109,151,157,171,197],"past":[2],"decade,":[3],"Field":[4],"Programmable":[5],"Gate":[6],"Arrays":[7],"(FPGA)":[8],"has":[9],"significantly":[10],"influenced":[11],"landscape":[13],"of":[14,23,33,52,63,73,122,173,199],"electronic":[16],"industry.":[17],"particular,":[19],"in":[20,40,177,190],"areas":[22],"semiconductor":[24],"manufacturing,":[25],"CAD":[26],"tool":[27],"designs":[28],"and":[29,81,125,142,165,195],"a":[30,70,114,174,178,200],"wide":[31,71],"range":[32,72],"digital":[34,57,61],"logic":[35],"applications.":[36,58],"Primarily,":[37],"research":[38],"efforts":[39],"FPGA":[42,64,132,137,176],"community":[43],"have":[44,160],"concentrated":[45],"on":[46,77,113],"improving":[47],"reconfigurability":[49],"or":[50,168],"programmability":[51],"present":[53],"day":[54],"architecture":[55,133,154,189],"for":[56,104,120,207],"However,":[59],"nature":[62],"technologies":[65],"limits":[66],"their":[67],"applicability":[68],"to":[69,159],"applications":[74],"that":[75,118,134,155],"depend":[76],"analog":[78],"circuitry,":[79],"photonic":[80,208],"RF":[82],"based":[83],"technologies.":[84],"As":[85],"with":[86,139,170],"any":[87],"ASIC":[88],"design,":[89],"turn-around":[91],"time":[92],"between":[93],"design":[94],"iterations":[95],"may":[96],"be":[97],"several":[98],"months":[99],"which":[100],"is":[101],"prohibitively":[102],"long":[103],"multi-technology":[105,144],"test-bed":[106],"systems":[107],"where":[108],"system":[110,126],"designer":[111],"depends":[112],"rapid":[115,162],"prototyping/experimentation":[116],"environment":[117,164],"allows":[119,156],"optimization":[121],"processing":[123],"algorithms":[124],"architecture.":[127],"Therefore,":[128],"we":[129,149],"developed":[130],"innovative":[131],"merges":[135],"conventional":[136,175],"technology":[138],"mixed":[140,179],"signal":[141,180],"other":[143],"device.":[145],"this":[147,184,188],"paper":[148],"discuss":[150],"Multi-Technology-FPGA":[152],"(MT-FPGA)":[153],"user":[158],"flexible":[161],"prototyping":[163],"provides":[166],"him":[167],"her":[169],"benefits":[172],"domain.":[181],"We":[182],"substantiate":[183],"concept":[185],"by":[186],"implementing":[187],"TSMC":[191],"0.35":[192],"\u03bcm":[193],"process":[194],"discussing":[196],"results":[198],"variable":[201],"threshold":[202],"optical":[203],"receiver":[204],"circuit":[205],"suitable":[206],"information":[209],"processing.":[210]},"counts_by_year":[],"updated_date":"2026-09-22T06:50:58.402377","created_date":"2016-06-24T00:00:00"}
