{"id":"https://openalex.org/W2063639637","doi":"https://doi.org/10.1145/17356.17401","title":"Highly concurrent scalar processing","display_name":"Highly concurrent scalar processing","publication_year":1986,"publication_date":"1986-05-01","ids":{"openalex":"https://openalex.org/W2063639637","doi":"https://doi.org/10.1145/17356.17401","mag":"2063639637"},"language":"en","primary_location":{"id":"doi:10.1145/17356.17401","doi":"https://doi.org/10.1145/17356.17401","is_oa":false,"landing_page_url":"https://doi.org/10.1145/17356.17401","pdf_url":null,"source":{"id":"https://openalex.org/S4210193905","display_name":"ACM SIGARCH Computer Architecture News","issn_l":"0163-5964","issn":["0163-5964","1943-5851"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","norway-1"],"host_organization":"https://openalex.org/P4310320740","host_organization_name":"ACM SIGARCH","host_organization_lineage":["https://openalex.org/P4310320740"],"host_organization_lineage_names":["ACM SIGARCH"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM SIGARCH Computer Architecture News","raw_type":"journal-article"},"volume":null,"type":"article","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"P. Y T Hsu","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4210114115","display_name":"IBM Research - Thomas J. Watson Research Center","ror":"https://ror.org/0265w5591","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"P. Y T Hsu","raw_affiliation_strings":["IBM T. J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IBM T. J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY","institution_ids":["https://openalex.org/I4210114115"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5025991850","display_name":"Edward S. Davidson","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"E. S. Davidson","raw_affiliation_strings":["Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, 1101 W. Springfield Ave., Urbana, Illinols","Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, 1101 W. Springfield Ave., Urbana, Illinols#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, 1101 W. Springfield Ave., Urbana, Illinols","institution_ids":["https://openalex.org/I157725225"]},{"raw_affiliation_string":"Computer Systems Group, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, 1101 W. Springfield Ave., Urbana, Illinols#TAB#","institution_ids":["https://openalex.org/I157725225"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":4.2268,"has_fulltext":false,"cited_by_count":214,"citation_normalized_percentile":{"value":0.93987521,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":87,"max":98},"biblio":{"volume":"14","issue":"2","first_page":"386","last_page":"395"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.0012000000569969416,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.0003000000142492354,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/instruction-scheduling","display_name":"instruction scheduling","score":0.671999990940094},{"id":"https://openalex.org/keywords/data-dependencies","display_name":"data dependencies","score":0.5709999799728394},{"id":"https://openalex.org/keywords/unix-kernel","display_name":"UNIX kernel","score":0.6019999980926514}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8645830154418945},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.842762291431427},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6518521308898926},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3322109878063202}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1145/17356.17401","doi":"https://doi.org/10.1145/17356.17401","is_oa":false,"landing_page_url":"https://doi.org/10.1145/17356.17401","pdf_url":null,"source":{"id":"https://openalex.org/S4210193905","display_name":"ACM SIGARCH Computer Architecture News","issn_l":"0163-5964","issn":["0163-5964","1943-5851"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","norway-1"],"host_organization":"https://openalex.org/P4310320740","host_organization_name":"ACM SIGARCH","host_organization_lineage":["https://openalex.org/P4310320740"],"host_organization_lineage_names":["ACM SIGARCH"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM SIGARCH Computer Architecture News","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.476.1411","doi":null,"is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.476.1411","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://mprc.pku.cn/mentors/training/ISCAreading/1986/p386-hsu/p386-hsu.pdf","raw_type":"text"},{"id":"pmh:ADA163195","doi":null,"is_oa":false,"landing_page_url":"http://oai.dtic.mil/oai/oai?&verb=getRecord&metadataPrefix=html&identifier=ADA163195","pdf_url":null,"source":{"id":"https://openalex.org/S4406923043","display_name":"Defense Technical Information Center (DTIC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"DTIC AND NTIS","raw_type":"Text"},{"id":"pmh:oai:www.ideals.illinois.edu:2142/88592","doi":null,"is_oa":false,"landing_page_url":"https://hdl.handle.net/2142/88592","pdf_url":null,"source":{"id":"https://openalex.org/S4306401358","display_name":"Illinois Digital Environment for Access to Learning and Scholarship (University of Illinois at Urbana-Champaign)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I2801919071","host_organization_name":"University of Illinois System","host_organization_lineage":["https://openalex.org/I2801919071"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W152254645","https://openalex.org/W634463279","https://openalex.org/W1500590019","https://openalex.org/W1522888794","https://openalex.org/W1580500750","https://openalex.org/W1969648707","https://openalex.org/W1977590451","https://openalex.org/W1987674899","https://openalex.org/W2002374396","https://openalex.org/W2005314217","https://openalex.org/W2011663807","https://openalex.org/W2015454481","https://openalex.org/W2033925885","https://openalex.org/W2042617557","https://openalex.org/W2058198174","https://openalex.org/W2063388447","https://openalex.org/W2066210260","https://openalex.org/W2098452744","https://openalex.org/W2122563027","https://openalex.org/W2128221687","https://openalex.org/W2129962996","https://openalex.org/W2130401729","https://openalex.org/W2144481293","https://openalex.org/W2154790323","https://openalex.org/W2154949349","https://openalex.org/W2170335116","https://openalex.org/W4240046008","https://openalex.org/W6653314688","https://openalex.org/W6678438195"],"related_works":["https://openalex.org/W2114048016","https://openalex.org/W53847210","https://openalex.org/W4250948896","https://openalex.org/W2065459284","https://openalex.org/W2040496724","https://openalex.org/W7100478771","https://openalex.org/W2092463181","https://openalex.org/W4230464011","https://openalex.org/W7096387467","https://openalex.org/W2128194410"],"abstract_inverted_index":{"High":[0],"speed":[1],"scalar":[2,19,94],"processing":[3],"is":[4,21,101],"an":[5,33],"essential":[6],"characteristic":[7],"of":[8,18,43,64,73,78,99,115],"high":[9],"performance":[10],"general":[11],"purpose":[12],"computer":[13],"systems.":[14],"Highly":[15],"concurrent":[16],"execution":[17],"code":[20,51,95],"difficult":[22,93],"due":[23],"to":[24,39,69],"data":[25],"dependencies":[26],"and":[27,112],"conditional":[28,44],"branches.":[29],"This":[30],"paper":[31],"proposes":[32],"architectural":[34],"concept":[35],"called":[36],"guarded":[37,74],"instructions":[38,60],"reduce":[40],"the":[41,54,87],"penalty":[42],"branches":[45],"in":[46,61],"deeply":[47],"pipelined":[48,106],"processors.":[49],"A":[50],"generation":[52],"heuristic,":[53],"decision":[55],"tree":[56],"scheduling":[57],"technique,":[58],"reorders":[59],"a":[62,84,97,113],"complex":[63],"basic":[65],"blocks":[66],"so":[67],"as":[68],"make":[70],"efficient":[71],"use":[72],"instructions.":[75],"Performance":[76],"evaluation":[77],"several":[79],"benchmarks":[80],"are":[81],"presented,":[82],"including":[83],"module":[85],"from":[86],"UNIX":[88],"kernel.":[89],"Even":[90],"with":[91,124],"these":[92],"examples,":[96],"speedup":[98,114],"two":[100],"achievable":[102],"by":[103,109],"using":[104,122],"conventional":[105],"uniprocessors":[107],"augmented":[108],"guard":[110],"instructions,":[111],"three":[116],"or":[117],"more":[118],"can":[119],"be":[120],"achieved":[121],"processors":[123],"parallel":[125],"instruction":[126],"pipelines.":[127]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":5}],"updated_date":"2026-11-12T12:28:57.059296","created_date":"2016-06-24T00:00:00"}