{"id":"https://openalex.org/W2060469151","doi":"https://doi.org/10.1109/isscc.1973.1155212","title":"A one-transistor memory cell with nondestructive readout","display_name":"A one-transistor memory cell with nondestructive readout","publication_year":1973,"publication_date":"1973-01-01","ids":{"openalex":"https://openalex.org/W2060469151","doi":"https://doi.org/10.1109/isscc.1973.1155212","mag":"2060469151"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.1973.1155212","doi":"https://doi.org/10.1109/isscc.1973.1155212","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.1973.1155212","pdf_url":null,"source":{"id":"https://openalex.org/S4210210374","display_name":"Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference","issn_l":"0193-6530","issn":["0193-6530","2376-8606"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","norway-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"1973 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5080115257","display_name":"William G. Oldham","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"W. Oldham","raw_affiliation_strings":["University of California, Berkeley, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of California, Berkeley, CA, USA","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061117258","display_name":"Stefan Cserveny","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"S. Cserveny","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5033302347","display_name":"H. Sigmund","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"H. Sigmund","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":5.2193,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.96261682,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"34","last_page":"35"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.6309000253677368,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.6309000253677368,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.23819999396800995,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.04540000110864639,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/nondestructive-readout","display_name":"nondestructive readout","score":0.972000002861023},{"id":"https://openalex.org/keywords/dynamic-memory","display_name":"dynamic memory","score":0.7089999914169312},{"id":"https://openalex.org/keywords/bipolar-junction-transistors","display_name":"bipolar transistors","score":0.781000018119812}],"concepts":[{"id":"https://openalex.org/C2777402240","wikidata":"https://www.wikidata.org/wiki/Q6783436","display_name":"Masking (illustration)","level":2,"score":0.6844317317008972},{"id":"https://openalex.org/C23061349","wikidata":"https://www.wikidata.org/wiki/Q188946","display_name":"Bipolar junction transistor","level":4,"score":0.6462260484695435},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.6119061708450317},{"id":"https://openalex.org/C2776638159","wikidata":"https://www.wikidata.org/wiki/Q18343761","display_name":"Memory cell","level":4,"score":0.5909218788146973},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.540269672870636},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.525844395160675},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.44937825202941895},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.44888392090797424},{"id":"https://openalex.org/C198352243","wikidata":"https://www.wikidata.org/wiki/Q37105","display_name":"Line (geometry)","level":2,"score":0.4387276768684387},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.42276063561439514},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3942663371562958},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3749238848686218},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3515591025352478},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.19372665882110596},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.1912463903427124},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18921539187431335},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.1973.1155212","doi":"https://doi.org/10.1109/isscc.1973.1155212","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.1973.1155212","pdf_url":null,"source":{"id":"https://openalex.org/S4210210374","display_name":"Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference","issn_l":"0193-6530","issn":["0193-6530","2376-8606"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","norway-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"1973 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2146569998","https://openalex.org/W4251802337","https://openalex.org/W4231612176","https://openalex.org/W1986580726","https://openalex.org/W2030847414","https://openalex.org/W2134935525","https://openalex.org/W1982196071","https://openalex.org/W1992893494","https://openalex.org/W2135052086","https://openalex.org/W1996984920"],"abstract_inverted_index":{"This":[0],"paper":[1],"will":[2],"describe":[3],"a":[4,16],"dynamic":[5],"high-speed":[6],"three-line":[7],"access":[8],"memory":[9],"cell":[10],"which":[11],"occupies":[12],"the":[13,28],"area":[14],"of":[15,30],"single":[17],"bipolar":[18,25],"transistor.":[19],"New":[20],"design":[21],"is":[22],"compatible":[23],"with":[24,27],"processing,":[26],"addition":[29],"one":[31],"extra":[32],"masking":[33],"step.":[34]},"counts_by_year":[],"updated_date":"2026-10-14T16:39:01.820549","created_date":"2016-06-24T00:00:00"}
