{"id":"https://openalex.org/W2052347697","doi":"https://doi.org/10.1109/54.43079","title":"Ideas: a tool for VLSI CAD","display_name":"Ideas: a tool for VLSI CAD","publication_year":1989,"publication_date":"1989-10-01","ids":{"openalex":"https://openalex.org/W2052347697","doi":"https://doi.org/10.1109/54.43079","mag":"2052347697"},"language":"en","primary_location":{"id":"doi:10.1109/54.43079","doi":"https://doi.org/10.1109/54.43079","is_oa":false,"landing_page_url":"https://doi.org/10.1109/54.43079","pdf_url":null,"source":{"id":"https://openalex.org/S73404582","display_name":"IEEE Design & Test of Computers","issn_l":"0740-7475","issn":["0740-7475","1558-1918"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design &amp; Test of Computers","raw_type":"journal-article"},"volume":null,"type":"article","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006752074","display_name":"Alok Kumar","orcid":"https://orcid.org/0000-0002-5554-6612","observed_orcids":["https://orcid.org/0000-0002-5554-6612","https://orcid.org/0009-0007-7017-2587"]},"institutions":[{"id":"https://openalex.org/I68891433","display_name":"Indian Institute of Technology Delhi","ror":"https://ror.org/049tgcd06","country_code":"IN","type":"education","lineage":["https://openalex.org/I68891433"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Alok Kumar","raw_affiliation_strings":["IIT Delhi","IIT Delhi, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IIT Delhi","institution_ids":["https://openalex.org/I68891433"]},{"raw_affiliation_string":"IIT Delhi, India","institution_ids":["https://openalex.org/I68891433"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032387954","display_name":"Vijeta Kashyap","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Vijeta Kashyap","raw_affiliation_strings":["Semiconductor Complex Limited, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Semiconductor Complex Limited, India","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029423576","display_name":"Sunil D. Sherlekar","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"S.D. Sherlekar","raw_affiliation_strings":["IIT Bombay, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IIT Bombay, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103247231","display_name":"G. Venkatesh","orcid":"https://orcid.org/0009-0004-8691-1573","observed_orcids":["https://orcid.org/0009-0004-8691-1573"]},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"G. Venkatesh","raw_affiliation_strings":["IIT Bombay, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IIT Bombay, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004660623","display_name":"S. Biwas","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"S. Biwas","raw_affiliation_strings":["IIT Bombay"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IIT Bombay","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101478917","display_name":"Anshul Kumar","orcid":"https://orcid.org/0000-0002-3871-5402","observed_orcids":["https://orcid.org/0000-0002-3871-5402"]},"institutions":[{"id":"https://openalex.org/I68891433","display_name":"Indian Institute of Technology Delhi","ror":"https://ror.org/049tgcd06","country_code":"IN","type":"education","lineage":["https://openalex.org/I68891433"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Anshul Kumar","raw_affiliation_strings":["IIT Delhi","IIT Delhi, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IIT Delhi","institution_ids":["https://openalex.org/I68891433"]},{"raw_affiliation_string":"IIT Delhi, India","institution_ids":["https://openalex.org/I68891433"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006039212","display_name":"P.C.P. Bhatt","orcid":"https://orcid.org/0000-0001-7356-4868","observed_orcids":["https://orcid.org/0000-0001-7356-4868"]},"institutions":[{"id":"https://openalex.org/I68891433","display_name":"Indian Institute of Technology Delhi","ror":"https://ror.org/049tgcd06","country_code":"IN","type":"education","lineage":["https://openalex.org/I68891433"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"P.C.P. Bhatt","raw_affiliation_strings":["IIT Delhi"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IIT Delhi","institution_ids":["https://openalex.org/I68891433"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110100222","display_name":"Sashi Kumar","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I68891433","display_name":"Indian Institute of Technology Delhi","ror":"https://ror.org/049tgcd06","country_code":"IN","type":"education","lineage":["https://openalex.org/I68891433"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sashi Kumar","raw_affiliation_strings":["IIT Delhi"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IIT Delhi","institution_ids":["https://openalex.org/I68891433"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.8456,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.82295139,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"6","issue":"5","first_page":"50","last_page":"57"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.5884000062942505,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.5884000062942505,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.40720000863075256,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11450","display_name":"Model-Driven Software Engineering Techniques","score":0.0008999999845400453,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vlsi-design-automation","display_name":"VLSI design automation","score":0.8299999833106995},{"id":"https://openalex.org/keywords/microcode-generation","display_name":"microcode generation","score":0.8489999771118164}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6537773609161377},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.5781974792480469},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.5458543300628662},{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.5297861099243164},{"id":"https://openalex.org/C2776639384","wikidata":"https://www.wikidata.org/wiki/Q840396","display_name":"Ideal (ethics)","level":2,"score":0.5001106262207031},{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.4821169376373291},{"id":"https://openalex.org/C21442007","wikidata":"https://www.wikidata.org/wiki/Q1027879","display_name":"Graphics","level":2,"score":0.47913500666618347},{"id":"https://openalex.org/C74193536","wikidata":"https://www.wikidata.org/wiki/Q574844","display_name":"Kernel (algebra)","level":2,"score":0.46723538637161255},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4322347044944763},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.35349684953689575},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3506350517272949},{"id":"https://openalex.org/C121684516","wikidata":"https://www.wikidata.org/wiki/Q7600677","display_name":"Computer graphics (images)","level":1,"score":0.22552135586738586},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.21040800213813782},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1909702718257904},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/54.43079","doi":"https://doi.org/10.1109/54.43079","is_oa":false,"landing_page_url":"https://doi.org/10.1109/54.43079","pdf_url":null,"source":{"id":"https://openalex.org/S73404582","display_name":"IEEE Design & Test of Computers","issn_l":"0740-7475","issn":["0740-7475","1558-1918"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Design &amp; Test of Computers","raw_type":"journal-article"},{"id":"pmh:oai:dsapce.library.iitb.ac.in:10054/8144","doi":null,"is_oa":false,"landing_page_url":"http://doi.org/10.1109/54.43079","pdf_url":null,"source":{"id":"https://openalex.org/S4306400899","display_name":"DSpace (IIT Bombay)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I162827531","host_organization_name":"Indian Institute of Technology Bombay","host_organization_lineage":["https://openalex.org/I162827531"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W1589047548","https://openalex.org/W2090435138","https://openalex.org/W4233643730"],"related_works":["https://openalex.org/W2565288555","https://openalex.org/W3168177894","https://openalex.org/W2033279237","https://openalex.org/W2005318194","https://openalex.org/W184923083","https://openalex.org/W45622134","https://openalex.org/W2978553495","https://openalex.org/W2028337929","https://openalex.org/W4240066141","https://openalex.org/W1584923579"],"abstract_inverted_index":{"The":[0],"authors":[1],"describe":[2],"the":[3],"Ideas":[4,13,43],"integrated":[5],"design":[6,26],"automation":[7,27],"system":[8],"being":[9],"developed":[10],"in":[11],"India.":[12],"is":[14,44],"based":[15],"on":[16,46],"a":[17,53,58,62,68],"new":[18],"high-level":[19],"hardware":[20],"description":[21],"language,":[22],"called":[23],"Ideal":[24],"(integrated":[25],"language),":[28],"which":[29],"incorporates":[30],"several":[31],"features":[32],"that":[33,60],"allow":[34],"it":[35],"to":[36],"model":[37],"both":[38],"event-driven":[39],"and":[40,50,65,71],"demand-driven":[41],"behavior.":[42],"built":[45],"an":[47],"object-oriented":[48],"kernel":[49],"consists":[51],"of":[52],"text-graphics":[54],"front-end":[55],"for":[56],"Ideal,":[57],"simulator":[59],"uses":[61],"mixed":[63],"interpretive":[64],"compiled":[66],"mode,":[67],"microcode":[69],"generator,":[70],"layout":[72],"tools.>":[73]},"counts_by_year":[],"updated_date":"2026-11-04T10:54:05.112534","created_date":"2016-06-24T00:00:00"}
