{"id":"https://openalex.org/W2033508089","doi":"https://doi.org/10.1145/17356.17399","title":"Software-controlled caches in the VMP multiprocessor","display_name":"Software-controlled caches in the VMP multiprocessor","publication_year":1986,"publication_date":"1986-05-01","ids":{"openalex":"https://openalex.org/W2033508089","doi":"https://doi.org/10.1145/17356.17399","mag":"2033508089"},"language":"en","primary_location":{"id":"doi:10.1145/17356.17399","doi":"https://doi.org/10.1145/17356.17399","is_oa":false,"landing_page_url":"https://doi.org/10.1145/17356.17399","pdf_url":null,"source":{"id":"https://openalex.org/S4210193905","display_name":"ACM SIGARCH Computer Architecture News","issn_l":"0163-5964","issn":["0163-5964","1943-5851"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","norway-1"],"host_organization":"https://openalex.org/P4310320740","host_organization_name":"ACM SIGARCH","host_organization_lineage":["https://openalex.org/P4310320740"],"host_organization_lineage_names":["ACM SIGARCH"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM SIGARCH Computer Architecture News","raw_type":"journal-article"},"volume":null,"type":"article","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5032416534","display_name":"David R. Cheriton","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D. R. Cheriton","raw_affiliation_strings":["Stanford University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Stanford University","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055575742","display_name":"Gert A. Slavenburg","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4210122849","display_name":"Philips (Netherlands)","ror":"https://ror.org/02p2bgp27","country_code":"NL","type":"company","lineage":["https://openalex.org/I4210122849"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"G. A. Slavenburg","raw_affiliation_strings":["Philips Research"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Philips Research","institution_ids":["https://openalex.org/I4210122849"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5082377198","display_name":"Patrick D. Boyle","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"P. D. Boyle","raw_affiliation_strings":["Stanford University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Stanford University","institution_ids":["https://openalex.org/I97018004"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":7.5144,"has_fulltext":false,"cited_by_count":79,"citation_normalized_percentile":{"value":0.96993761,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":88,"max":95},"biblio":{"volume":"14","issue":"2","first_page":"366","last_page":"374"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.00019999999494757503,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.00019999999494757503,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cache-misses","display_name":"cache misses","score":0.6520000100135803},{"id":"https://openalex.org/keywords/cache-consistency","display_name":"cache consistency","score":0.8379999995231628},{"id":"https://openalex.org/keywords/shared-bus","display_name":"shared bus","score":0.4869999885559082},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"memory bandwidth","score":0.9330000281333923},{"id":"https://openalex.org/keywords/virtual-addressing","display_name":"virtual addressing","score":0.531000018119812},{"id":"https://openalex.org/keywords/data-contention","display_name":"data contention","score":0.5849999785423279}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8574569225311279},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.7435970306396484},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6941672563552856},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.657280445098877},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.6315255165100098},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.6253804564476013},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5984004139900208},{"id":"https://openalex.org/C120936851","wikidata":"https://www.wikidata.org/wiki/Q1408065","display_name":"MESI protocol","level":5,"score":0.5895266532897949},{"id":"https://openalex.org/C25536678","wikidata":"https://www.wikidata.org/wiki/Q5015977","display_name":"Cache invalidation","level":5,"score":0.5714980363845825},{"id":"https://openalex.org/C51185590","wikidata":"https://www.wikidata.org/wiki/Q1017228","display_name":"Bus sniffing","level":5,"score":0.5472251772880554},{"id":"https://openalex.org/C36340418","wikidata":"https://www.wikidata.org/wiki/Q7124288","display_name":"Page cache","level":5,"score":0.5249260067939758},{"id":"https://openalex.org/C167713795","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"Smart Cache","level":5,"score":0.45640647411346436},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.45000576972961426},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.41756996512413025},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4145428538322449},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3431972563266754}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/17356.17399","doi":"https://doi.org/10.1145/17356.17399","is_oa":false,"landing_page_url":"https://doi.org/10.1145/17356.17399","pdf_url":null,"source":{"id":"https://openalex.org/S4210193905","display_name":"ACM SIGARCH Computer Architecture News","issn_l":"0163-5964","issn":["0163-5964","1943-5851"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","norway-1"],"host_organization":"https://openalex.org/P4310320740","host_organization_name":"ACM SIGARCH","host_organization_lineage":["https://openalex.org/P4310320740"],"host_organization_lineage_names":["ACM SIGARCH"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM SIGARCH Computer Architecture News","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1480232631","https://openalex.org/W1964602554","https://openalex.org/W1982326628","https://openalex.org/W1986209913","https://openalex.org/W1990759612","https://openalex.org/W2021817036","https://openalex.org/W2049142403","https://openalex.org/W2051416929","https://openalex.org/W2120837116","https://openalex.org/W2130360419","https://openalex.org/W2131791649","https://openalex.org/W2157511281","https://openalex.org/W2158365276","https://openalex.org/W2170830522","https://openalex.org/W2294693415","https://openalex.org/W3159585669","https://openalex.org/W4230076379","https://openalex.org/W6677666987","https://openalex.org/W6683379451"],"related_works":["https://openalex.org/W2133806301","https://openalex.org/W2150757057","https://openalex.org/W4246062738","https://openalex.org/W1523978917","https://openalex.org/W2011544386","https://openalex.org/W2167870783","https://openalex.org/W4301657354","https://openalex.org/W2087142734","https://openalex.org/W2339199727","https://openalex.org/W2021817036"],"abstract_inverted_index":{"VMP":[0,110],"is":[1,81,101,156],"an":[2],"experimental":[3],"multiprocessor":[4],"that":[5,88,147],"follows":[6],"the":[7,69,90,94,109,113,136,148],"familiar":[8],"basic":[9],"design":[10,111,149],"of":[11,71,125],"multiple":[12],"processors,":[13],"each":[14],"with":[15,122,140],"a":[16,20,29,84,97,123],"cache,":[17,38],"connected":[18],"by":[19,118],"shared":[21],"bus":[22,91],"to":[23,36,62,68,83,135],"global":[24],"memory.":[25],"Each":[26],"processor":[27,95],"has":[28],"synchronous,":[30],"virtually":[31,141],"addressed,":[32],"single":[33],"master":[34],"connection":[35],"its":[37],"providing":[39,153],"very":[40],"high":[41,114],"memory":[42,53,73,115],"bandwidth.":[43],"An":[44],"unusually":[45],"large":[46],"cache":[47,60,79,98],"page":[48,74],"size":[49],"and":[50,92,128],"fast":[51],"sequential":[52],"copy":[54],"hardware":[55,126],"make":[56],"it":[57],"feasible":[58],"for":[59,78],"misses":[61],"be":[63],"handled":[64],"in":[65],"software,":[66],"analogously":[67],"handling":[70],"virtual":[72],"faults.":[75],"Hardware":[76],"support":[77],"consistency":[80,99,137],"limited":[82],"simple":[85,133],"state":[86],"machine":[87],"monitors":[89],"interrupts":[93],"when":[96],"action":[100],"required.":[102],"In":[103],"this":[104],"paper,":[105],"we":[106],"show":[107],"how":[108],"provides":[112],"bandwidth":[116],"required":[117],"modern":[119],"high-performance":[120],"processors":[121],"minimum":[124],"complexity":[127],"cost.":[129],"We":[130],"also":[131],"describe":[132],"solutions":[134],"problems":[138],"associated":[139],"addressed":[142],"caches.":[143],"Simulation":[144],"results":[145],"indicate":[146],"achieves":[150],"good":[151],"performance":[152],"data":[154],"contention":[155],"not":[157],"excessive.":[158]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2026-11-07T11:25:07.637180","created_date":"2016-06-24T00:00:00"}