{"id":"https://openalex.org/W2021040705","doi":"https://doi.org/10.1049/ip-cds:20030574","title":"High-performance FPGA implementation of DES using a novel method for implementing the key schedule","display_name":"High-performance FPGA implementation of DES using a novel method for implementing the key schedule","publication_year":2003,"publication_date":"2003-01-01","ids":{"openalex":"https://openalex.org/W2021040705","doi":"https://doi.org/10.1049/ip-cds:20030574","mag":"2021040705"},"language":"en","primary_location":{"id":"doi:10.1049/ip-cds:20030574","doi":"https://doi.org/10.1049/ip-cds:20030574","is_oa":false,"landing_page_url":"https://doi.org/10.1049/ip-cds:20030574","pdf_url":null,"source":{"id":"https://openalex.org/S4210173989","display_name":"IEE Proceedings - Circuits Devices and Systems","issn_l":"1350-2409","issn":["1350-2409","1359-7000"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","norway-1"],"host_organization":"https://openalex.org/P4310311714","host_organization_name":"Institution of Engineering and Technology","host_organization_lineage":["https://openalex.org/P4310311714"],"host_organization_lineage_names":["Institution of Engineering and Technology"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEE Proceedings - Circuits, Devices and Systems","raw_type":"journal-article"},"volume":null,"type":"article","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5011754647","display_name":"M. McLoone","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I126231945","display_name":"Queen's University Belfast","ror":"https://ror.org/00hswnk62","country_code":"GB","type":"education","lineage":["https://openalex.org/I126231945"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"M. McLoone","raw_affiliation_strings":["School of Electrical and Electronic Engineering, DSiP\u2122 Laboratories, Queen's University of Belfast, Belfast, UK","School of Electronics, Electrical Engineering and Computer Science, Secure Digital Systems (SDS)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, DSiP\u2122 Laboratories, Queen's University of Belfast, Belfast, UK","institution_ids":["https://openalex.org/I126231945"]},{"raw_affiliation_string":"School of Electronics, Electrical Engineering and Computer Science, Secure Digital Systems (SDS)","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111565223","display_name":"John V McCanny","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I126231945","display_name":"Queen's University Belfast","ror":"https://ror.org/00hswnk62","country_code":"GB","type":"education","lineage":["https://openalex.org/I126231945"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"J.V. McCanny","raw_affiliation_strings":["School of Electrical and Electronic Engineering, DSiP\u2122 Laboratories, Queen's University of Belfast, Belfast, UK","Sch. of Electr. & Electron. Eng., Queen's Univ. Belfast, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, DSiP\u2122 Laboratories, Queen's University of Belfast, Belfast, UK","institution_ids":["https://openalex.org/I126231945"]},{"raw_affiliation_string":"Sch. of Electr. & Electron. Eng., Queen's Univ. Belfast, UK","institution_ids":["https://openalex.org/I126231945"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I126231945"],"apc_list":null,"apc_paid":null,"fwci":0.3469,"has_fulltext":false,"cited_by_count":53,"citation_normalized_percentile":{"value":0.6880125,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":88,"max":99},"biblio":{"volume":"150","issue":"5","first_page":"373","last_page":"373"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.00019999999494757503,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11693","display_name":"Cryptography and Residue Arithmetic","score":0.00019999999494757503,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/data-encryption-standard","display_name":"Data Encryption Standard","score":0.878000020980835},{"id":"https://openalex.org/keywords/des","display_name":"DES","score":0.5149999856948853},{"id":"https://openalex.org/keywords/key-scheduling","display_name":"key scheduling","score":0.7360000014305115},{"id":"https://openalex.org/keywords/fpga-implementation","display_name":"FPGA implementation","score":0.9430000185966492},{"id":"https://openalex.org/keywords/pipelined-hardware","display_name":"pipelined hardware","score":0.6970000267028809},{"id":"https://openalex.org/keywords/symmetric-encryption","display_name":"symmetric encryption","score":0.9089999794960022},{"id":"https://openalex.org/keywords/hardware-acceleration","display_name":"hardware acceleration","score":0.5929999947547913},{"id":"https://openalex.org/keywords/xilinx-virtex","display_name":"Xilinx Virtex","score":0.800000011920929}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8188697695732117},{"id":"https://openalex.org/C148730421","wikidata":"https://www.wikidata.org/wiki/Q141090","display_name":"Encryption","level":2,"score":0.7426102161407471},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7327454090118408},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.6166932582855225},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.6041786074638367},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.6038020253181458},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5429233908653259},{"id":"https://openalex.org/C61719626","wikidata":"https://www.wikidata.org/wiki/Q17081362","display_name":"Disk encryption hardware","level":5,"score":0.5409762263298035},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5323811769485474},{"id":"https://openalex.org/C2983609787","wikidata":"https://www.wikidata.org/wiki/Q10534782","display_name":"Software implementation","level":3,"score":0.437394917011261},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.42491692304611206},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.34337636828422546},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3267386555671692},{"id":"https://openalex.org/C203062551","wikidata":"https://www.wikidata.org/wiki/Q201339","display_name":"Public-key cryptography","level":3,"score":0.23106971383094788},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.21975207328796387},{"id":"https://openalex.org/C46905813","wikidata":"https://www.wikidata.org/wiki/Q4640678","display_name":"56-bit encryption","level":4,"score":0.16590937972068787},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08627042174339294},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.08143073320388794},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1049/ip-cds:20030574","doi":"https://doi.org/10.1049/ip-cds:20030574","is_oa":false,"landing_page_url":"https://doi.org/10.1049/ip-cds:20030574","pdf_url":null,"source":{"id":"https://openalex.org/S4210173989","display_name":"IEE Proceedings - Circuits Devices and Systems","issn_l":"1350-2409","issn":["1350-2409","1359-7000"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","norway-1"],"host_organization":"https://openalex.org/P4310311714","host_organization_name":"Institution of Engineering and Technology","host_organization_lineage":["https://openalex.org/P4310311714"],"host_organization_lineage_names":["Institution of Engineering and Technology"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEE Proceedings - Circuits, Devices and Systems","raw_type":"journal-article"},{"id":"pmh:oai:pure.qub.ac.uk/portal:publications/e9b5f55a-0bd2-438d-8925-cbcc6ad23659","doi":null,"is_oa":false,"landing_page_url":"https://pure.qub.ac.uk/en/publications/e9b5f55a-0bd2-438d-8925-cbcc6ad23659","pdf_url":null,"source":{"id":"https://openalex.org/S4306402319","display_name":"Research Portal (Queen's University Belfast)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I126231945","host_organization_name":"Queen's University Belfast","host_organization_lineage":["https://openalex.org/I126231945"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"McLoone, M & McCanny, J V 2003, 'High-performance FPGA implementation of DES using a novel method for implementing the key schedule', IEE Proceedings - Circuits, Devices and Systems, vol. 150, no. 5, pp. 373-378. https://doi.org/10.1049/ip-cds:20030574","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.5378999710083008}],"study_designs":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320338080","display_name":"European Social Fund","ror":"https://ror.org/00k4n6c32"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1499050268","https://openalex.org/W1548516269","https://openalex.org/W1596766545","https://openalex.org/W1660562555","https://openalex.org/W1916681597","https://openalex.org/W2130029613","https://openalex.org/W6636975353"],"related_works":["https://openalex.org/W2288362869","https://openalex.org/W2124134801","https://openalex.org/W2391997288","https://openalex.org/W2356320136","https://openalex.org/W2253482281","https://openalex.org/W3005827483","https://openalex.org/W2534978633","https://openalex.org/W2471525587","https://openalex.org/W2020908188","https://openalex.org/W2952372344"],"abstract_inverted_index":{"A":[0],"generic,":[1],"parameterisable":[2],"key":[3,35],"scheduling":[4,36],"core":[5],"is":[6,29,49,54,70,84,91],"presented,":[7],"which":[8,23,72],"can":[9,73],"be":[10],"utilised":[11,30],"in":[12],"pipelinable":[13],"private-key":[14],"encryption":[15,19,47,77],"algorithms.":[16],"The":[17,51],"data":[18],"standard":[20],"(DES)":[21],"algorithm,":[22],"lends":[24],"itself":[25],"readily":[26],"to":[27,31,45],"pipelining,":[28],"exemplify":[32],"this":[33],"novel":[34,63],"method":[37,44],"and":[38,90],"the":[39,43,62,86],"broader":[40],"applicability":[41],"of":[42,79],"other":[46],"algorithms":[48],"illustrated.":[50],"DES":[52,68],"design":[53,69],"implemented":[55],"on":[56],"Xilinx":[57],"Virtex":[58],"FPGA":[59],"technology.":[60],"Utilising":[61],"method,":[64],"a":[65,92],"16-stage":[66],"pipelined":[67],"achieved,":[71],"run":[74],"at":[75],"an":[76],"rate":[78],"3.87":[80],"Gbit/s.":[81],"This":[82],"result":[83],"among":[85],"fastest":[87],"hardware":[88],"implementations":[89],"factor":[93],"28":[94],"times":[95],"faster":[96],"than":[97],"software":[98],"implementations.":[99]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":5},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":8},{"year":2016,"cited_by_count":5},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":6}],"updated_date":"2026-10-29T09:56:32.521200","created_date":"2016-06-24T00:00:00"}