{"id":"https://openalex.org/W2020351673","doi":"https://doi.org/10.1109/ewdts.2013.6673185","title":"Architecture of built-in self-test and recovery memory chips","display_name":"Architecture of built-in self-test and recovery memory chips","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W2020351673","doi":"https://doi.org/10.1109/ewdts.2013.6673185","mag":"2020351673"},"language":"en","primary_location":{"id":"doi:10.1109/ewdts.2013.6673185","doi":"https://doi.org/10.1109/ewdts.2013.6673185","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2013.6673185","pdf_url":null,"source":{"id":"https://openalex.org/S7407087784","display_name":"IEEE East-West Design & Test Symposium (EWDTS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"East-West Design & Test Symposium (EWDTS 2013)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"V.A. Andrienko","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4210108895","display_name":"Cherkasy State Technological University","ror":"https://ror.org/01m54ds80","country_code":"UA","type":"education","lineage":["https://openalex.org/I4210108895"]}],"countries":["UA"],"is_corresponding":false,"raw_author_name":"V.A. Andrienko","raw_affiliation_strings":["Cherkassy State Technological University","Cherkassy State Technol. Univ., Cherkasy, Ukraine"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cherkassy State Technological University","institution_ids":["https://openalex.org/I4210108895"]},{"raw_affiliation_string":"Cherkassy State Technol. Univ., Cherkasy, Ukraine","institution_ids":["https://openalex.org/I4210108895"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059114961","display_name":"Diaa Moamar","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4210108895","display_name":"Cherkasy State Technological University","ror":"https://ror.org/01m54ds80","country_code":"UA","type":"education","lineage":["https://openalex.org/I4210108895"]}],"countries":["UA"],"is_corresponding":false,"raw_author_name":"Moamar Diaa","raw_affiliation_strings":["Cherkassy State Technological University","Cherkassy State Technol. Univ., Cherkasy, Ukraine"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cherkassy State Technological University","institution_ids":["https://openalex.org/I4210108895"]},{"raw_affiliation_string":"Cherkassy State Technol. Univ., Cherkasy, Ukraine","institution_ids":["https://openalex.org/I4210108895"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109274295","display_name":"Vladimir Ryabtsev","orcid":"https://orcid.org/0000-0002-0592-2413","observed_orcids":["https://orcid.org/0000-0002-0592-2413","https://orcid.org/0000-0001-5243-7923"]},"institutions":[{"id":"https://openalex.org/I4210133108","display_name":"European University","ror":"https://ror.org/032s10s29","country_code":"UA","type":"education","lineage":["https://openalex.org/I4210133108"]}],"countries":["UA"],"is_corresponding":false,"raw_author_name":"V.G. Ryabtsev","raw_affiliation_strings":["Cherkassy branch of the European University","Cherkassy Branch of the Eur. Univ., Cherkasy, Ukraine"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cherkassy branch of the European University","institution_ids":["https://openalex.org/I4210133108"]},{"raw_affiliation_string":"Cherkassy Branch of the Eur. Univ., Cherkasy, Ukraine","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5070153249","display_name":"Tetyana Utkina","orcid":"https://orcid.org/0000-0002-6614-4133","observed_orcids":["https://orcid.org/0000-0002-6614-4133"]},"institutions":[{"id":"https://openalex.org/I4210108895","display_name":"Cherkasy State Technological University","ror":"https://ror.org/01m54ds80","country_code":"UA","type":"education","lineage":["https://openalex.org/I4210108895"]}],"countries":["UA"],"is_corresponding":false,"raw_author_name":"T.Yu. Utkina","raw_affiliation_strings":["Cherkassy State Technological University","Cherkassy State Technol. Univ., Cherkasy, Ukraine"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cherkassy State Technological University","institution_ids":["https://openalex.org/I4210108895"]},{"raw_affiliation_string":"Cherkassy State Technol. Univ., Cherkasy, Ukraine","institution_ids":["https://openalex.org/I4210108895"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.1895,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.32330827,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":88,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"12"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9672999978065491,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9672999978065491,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.017000000923871994,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.00860000029206276,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"built-in self-test","score":0.9860000014305115},{"id":"https://openalex.org/keywords/memory-cell-array","display_name":"memory cell array","score":0.49399998784065247},{"id":"https://openalex.org/keywords/technical-readiness","display_name":"technical readiness","score":0.5640000104904175}],"concepts":[{"id":"https://openalex.org/C2780945871","wikidata":"https://www.wikidata.org/wiki/Q194274","display_name":"Backup","level":2,"score":0.7520122528076172},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7084911465644836},{"id":"https://openalex.org/C3017990537","wikidata":"https://www.wikidata.org/wiki/Q6815759","display_name":"Memory test","level":3,"score":0.6136643886566162},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6055719256401062},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.5538161396980286},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.5151444673538208},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.487792044878006},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.46195435523986816},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.46060970425605774},{"id":"https://openalex.org/C34172316","wikidata":"https://www.wikidata.org/wiki/Q499024","display_name":"Non-volatile random-access memory","level":5,"score":0.4576922357082367},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.44755059480667114},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.43208375573158264},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.4213344156742096},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4198254346847534},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.4194177985191345},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.40683597326278687},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.3374011516571045},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2547609210014343},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C169760540","wikidata":"https://www.wikidata.org/wiki/Q207011","display_name":"Neuroscience","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C169900460","wikidata":"https://www.wikidata.org/wiki/Q2200417","display_name":"Cognition","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ewdts.2013.6673185","doi":"https://doi.org/10.1109/ewdts.2013.6673185","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ewdts.2013.6673185","pdf_url":null,"source":{"id":"https://openalex.org/S7407087784","display_name":"IEEE East-West Design & Test Symposium (EWDTS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"East-West Design & Test Symposium (EWDTS 2013)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2079486027","https://openalex.org/W2111412828"],"related_works":["https://openalex.org/W4229821096","https://openalex.org/W2611855257","https://openalex.org/W3121995472","https://openalex.org/W2015754562","https://openalex.org/W4256298596","https://openalex.org/W2126481023","https://openalex.org/W3111962339","https://openalex.org/W2152272528","https://openalex.org/W1515138646","https://openalex.org/W2478679151"],"abstract_inverted_index":{"The":[0,14,56],"article":[1],"is":[2,21,40],"devoted":[3],"to":[4],"increasing":[5],"the":[6,30,38,43,47,65],"coefficient":[7],"of":[8,11,16,29,33,49,52,64,69],"technical":[9],"readiness":[10],"memory":[12,34,54],"chips.":[13],"architecture":[15],"built-in":[17],"self-test":[18],"and":[19,59],"repair":[20],"proposed,":[22],"what":[23],"allows":[24],"changing":[25],"a":[26],"bit":[27],"data":[28,44,66],"primary":[31],"array":[32,51],"cells,":[35],"in":[36],"which":[37],"failure":[39,68],"occurred,":[41],"on":[42],"coming":[45],"from":[46],"outputs":[48],"an":[50],"backup":[53],"cells.":[55],"proposed":[57],"hardware":[58],"software":[60],"provide":[61],"automatic":[62],"reconfiguration":[63],"upon":[67],"chip.":[70]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2016,"cited_by_count":1}],"updated_date":"2026-10-30T12:39:25.321706","created_date":"2016-06-24T00:00:00"}