{"id":"https://openalex.org/W2018997098","doi":"https://doi.org/10.1109/vlsid.2014.45","title":"Challenges in Implementing Cache-Based Side Channel Attacks on Modern Processors","display_name":"Challenges in Implementing Cache-Based Side Channel Attacks on Modern Processors","publication_year":2014,"publication_date":"2014-01-01","ids":{"openalex":"https://openalex.org/W2018997098","doi":"https://doi.org/10.1109/vlsid.2014.45","mag":"2018997098"},"language":"en","primary_location":{"id":"doi:10.1109/vlsid.2014.45","doi":"https://doi.org/10.1109/vlsid.2014.45","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsid.2014.45","pdf_url":null,"source":{"id":"https://openalex.org/S4306419912","display_name":"International Conference on VLSI Design","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5016619024","display_name":"Jyoti Gajrani","orcid":"https://orcid.org/0000-0002-8223-5975","observed_orcids":["https://orcid.org/0000-0002-8223-5975"]},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Jyoti Gajrani","raw_affiliation_strings":["Dept. of Comput. Sci. & Eng., Indian Inst. of Technol. Bombay, Mumbai, India","Department of Computer Science and Engineering, Indian Institute of Technology, Bombay Mumbai, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Comput. Sci. & Eng., Indian Inst. of Technol. Bombay, Mumbai, India","institution_ids":["https://openalex.org/I162827531"]},{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology, Bombay Mumbai, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031426546","display_name":"Pooja Mazumdar","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Pooja Mazumdar","raw_affiliation_strings":["Dept. of Comput. Sci. & Eng., Indian Inst. of Technol. Bombay, Mumbai, India","Department of Computer Science and Engineering, Indian Institute of Technology, Bombay Mumbai, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Comput. Sci. & Eng., Indian Inst. of Technol. Bombay, Mumbai, India","institution_ids":["https://openalex.org/I162827531"]},{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology, Bombay Mumbai, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066940281","display_name":"Sampreet A. Sharma","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sampreet Sharma","raw_affiliation_strings":["Dept. of Comput. Sci. & Eng., Indian Inst. of Technol. Bombay, Mumbai, India","Department of Computer Science and Engineering, Indian Institute of Technology, Bombay Mumbai, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Comput. Sci. & Eng., Indian Inst. of Technol. Bombay, Mumbai, India","institution_ids":["https://openalex.org/I162827531"]},{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology, Bombay Mumbai, India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5088605355","display_name":"Bernard L. Menezes","orcid":"https://orcid.org/0000-0003-2997-9286","observed_orcids":["https://orcid.org/0000-0003-2997-9286"]},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Bernard Menezes","raw_affiliation_strings":["Dept. of Comput. Sci. & Eng., Indian Inst. of Technol. Bombay, Mumbai, India","Department of Computer Science and Engineering, Indian Institute of Technology, Bombay Mumbai, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Comput. Sci. & Eng., Indian Inst. of Technol. Bombay, Mumbai, India","institution_ids":["https://openalex.org/I162827531"]},{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology, Bombay Mumbai, India","institution_ids":["https://openalex.org/I162827531"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I162827531"],"apc_list":null,"apc_paid":null,"fwci":0.1936,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.33575058,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":87,"max":93},"biblio":{"volume":null,"issue":null,"first_page":"222","last_page":"227"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11424","display_name":"Security and Verification in Computing","score":0.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11693","display_name":"Cryptography and Residue Arithmetic","score":0.0,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/advanced-encryption-standard","display_name":"Advanced Encryption Standard","score":0.7269999980926514},{"id":"https://openalex.org/keywords/aes","display_name":"AES","score":0.47699999809265137},{"id":"https://openalex.org/keywords/lookup-tables","display_name":"look-up table","score":0.5600000023841858},{"id":"https://openalex.org/keywords/virtual-machines","display_name":"virtual machines","score":0.5529999732971191},{"id":"https://openalex.org/keywords/cloud-security","display_name":"cloud security","score":0.7879999876022339},{"id":"https://openalex.org/keywords/key-recovery","display_name":"key recovery","score":0.6690000295639038},{"id":"https://openalex.org/keywords/timing-side-channel","display_name":"timing side channels","score":0.5690000057220459},{"id":"https://openalex.org/keywords/intel-core-2-duo","display_name":"Intel Core 2 Duo","score":0.7730000019073486}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8515236377716064},{"id":"https://openalex.org/C49289754","wikidata":"https://www.wikidata.org/wiki/Q2267081","display_name":"Side channel attack","level":3,"score":0.7893296480178833},{"id":"https://openalex.org/C94520183","wikidata":"https://www.wikidata.org/wiki/Q190746","display_name":"Advanced Encryption Standard","level":3,"score":0.6811765432357788},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.628569483757019},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.582236111164093},{"id":"https://openalex.org/C178489894","wikidata":"https://www.wikidata.org/wiki/Q8789","display_name":"Cryptography","level":2,"score":0.5309383869171143},{"id":"https://openalex.org/C46331935","wikidata":"https://www.wikidata.org/wiki/Q4651362","display_name":"AES implementations","level":4,"score":0.523082971572876},{"id":"https://openalex.org/C28420585","wikidata":"https://www.wikidata.org/wiki/Q2665075","display_name":"Timing attack","level":4,"score":0.5220606327056885},{"id":"https://openalex.org/C148730421","wikidata":"https://www.wikidata.org/wiki/Q141090","display_name":"Encryption","level":2,"score":0.48984572291374207},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.48794883489608765},{"id":"https://openalex.org/C71743495","wikidata":"https://www.wikidata.org/wiki/Q2845210","display_name":"Power analysis","level":3,"score":0.47966793179512024},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.45796823501586914},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.3867309093475342},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.29591894149780273},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2794531285762787}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsid.2014.45","doi":"https://doi.org/10.1109/vlsid.2014.45","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsid.2014.45","pdf_url":null,"source":{"id":"https://openalex.org/S4306419912","display_name":"International Conference on VLSI Design","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1488058190","https://openalex.org/W1496265857","https://openalex.org/W1556212265","https://openalex.org/W1994390420","https://openalex.org/W2050937543","https://openalex.org/W2103289002","https://openalex.org/W2126256517","https://openalex.org/W2131202839","https://openalex.org/W2159054268","https://openalex.org/W2169461225"],"related_works":["https://openalex.org/W2103289002","https://openalex.org/W1488058190","https://openalex.org/W2578489987","https://openalex.org/W7098564262","https://openalex.org/W6982404448","https://openalex.org/W2380122332","https://openalex.org/W1082807764","https://openalex.org/W2949489818","https://openalex.org/W2166293920","https://openalex.org/W2349411859"],"abstract_inverted_index":{"To":[0],"optimize":[1],"performance,":[2],"modern":[3],"processors":[4],"have":[5],"features":[6,22],"like":[7],"nonblocking":[8],"and":[9,52,68,126,193],"pipelined":[10],"caches":[11],"along":[12],"with":[13],"support":[14],"for":[15,95],"data/instruction":[16],"prefetching.":[17],"However,":[18],"some":[19],"of":[20,37,44,76,85,111,116,139,181],"these":[21],"inadvertently":[23],"thwart":[24],"carefully":[25],"designed":[26],"attacks":[27,32,40,80,100],"on":[28,152,156,161,185],"cryptographic":[29],"algorithms.":[30],"The":[31,99],"belong":[33],"to":[34,57,142,170],"the":[35,70,74,82,91,102,124,133,143,157,165,172,179,182,186],"class":[36],"side":[38,47,78],"channel":[39,79],"wherein":[41],"subtle":[42],"leakage":[43],"information":[45],"through":[46],"channels":[48],"such":[49],"as":[50],"power":[51],"timing":[53],"can":[54],"be":[55,150],"exploited":[56],"compromise":[58],"secret":[59,96],"keys":[60],"in":[61,73,114],"sensitive":[62],"applications.":[63],"This":[64,137],"paper":[65],"further":[66],"extends":[67],"modifies":[69],"existing":[71],"work":[72],"field":[75,118],"cache-based":[77],"targeting":[81],"software":[83],"implementation":[84],"Advanced":[86],"Encryption":[87],"Standard":[88],"(AES)":[89],"-":[90],"de":[92],"facto":[93],"standard":[94],"key":[97],"cryptography.":[98],"exploit":[101],"fact":[103],"that":[104,123],"each":[105],"AES":[106],"round":[107],"makes":[108],"extensive":[109],"use":[110],"lookup":[112],"tables":[113],"lieu":[115],"expensive":[117],"operations.":[119],"It":[120],"is":[121,138],"assumed":[122],"attacker":[125],"victim":[127],"(the":[128],"process":[129],"running":[130],"AES)":[131],"share":[132],"same":[134,158,166],"processor":[135],"cache.":[136,167],"special":[140],"relevance":[141],"cloud":[144],"environment":[145],"where":[146],"two":[147],"applications":[148],"may":[149],"hosted":[151],"different":[153,162],"virtual":[154],"machines":[155],"core":[159],"or":[160],"cores":[163],"sharing":[164],"In":[168],"addition":[169],"describing":[171],"challenges":[173],"encountered,":[174],"our":[175],"experimental":[176],"results":[177],"demonstrate":[178],"feasibility":[180],"modified":[183],"attack":[184],"Intel":[187],"Dual":[188],"Core,":[189],"Core":[190],"2":[191],"Duo":[192],"AMD":[194],"Athlon":[195],"X2.":[196]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-11-10T11:39:43.021295","created_date":"2016-06-24T00:00:00"}
