{"id":"https://openalex.org/W2017794672","doi":"https://doi.org/10.1109/isscc.1984.1156673","title":"A burst-mode LSI equalizer with analog-digital building blocks","display_name":"A burst-mode LSI equalizer with analog-digital building blocks","publication_year":1984,"publication_date":"1984-01-01","ids":{"openalex":"https://openalex.org/W2017794672","doi":"https://doi.org/10.1109/isscc.1984.1156673","mag":"2017794672"},"language":"en","primary_location":{"id":"doi:10.1109/isscc.1984.1156673","doi":"https://doi.org/10.1109/isscc.1984.1156673","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.1984.1156673","pdf_url":null,"source":{"id":"https://openalex.org/S4210210374","display_name":"Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference","issn_l":"0193-6530","issn":["0193-6530","2376-8606"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","norway-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5090429551","display_name":"Y. Hino","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I2252096349","display_name":"Fujitsu (Japan)","ror":"https://ror.org/038e2g226","country_code":"JP","type":"company","lineage":["https://openalex.org/I2252096349"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Y. Hino","raw_affiliation_strings":["Fujitsu, Ltd./Labs., Kawasaki, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Fujitsu, Ltd./Labs., Kawasaki, Japan","institution_ids":["https://openalex.org/I2252096349"]}]},{"author_position":"middle","author":{"id":null,"display_name":"T. Chujo","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"T. Chujo","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":null,"display_name":"N. Ueno","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"N. Ueno","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113626762","display_name":"K. Fujita","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"K. Fujita","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113939705","display_name":"M. Yamamoto","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"M. Yamamoto","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":null,"display_name":"K. Yamaguchi","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"K. Yamaguchi","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5077807337","display_name":"Hiroaki Kikuchi","orcid":"https://orcid.org/0000-0003-3636-8627","observed_orcids":["https://orcid.org/0000-0003-3636-8627"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"H. Kikuchi","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.9452,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.87260616,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"238","last_page":"239"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9125999808311462,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9125999808311462,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.04619999974966049,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.008700000122189522,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/digital-subscriber-loop","display_name":"digital subscriber loop","score":0.7300000190734863},{"id":"https://openalex.org/keywords/equalizer","display_name":"equalizer","score":0.7440000176429749},{"id":"https://openalex.org/keywords/burst-mode-operation","display_name":"burst mode operation","score":0.6809999942779541},{"id":"https://openalex.org/keywords/lsi","display_name":"LSI","score":0.5450000166893005},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5460000038146973},{"id":"https://openalex.org/keywords/automatic-gain-control","display_name":"automatic gain control","score":0.8109999895095825}],"concepts":[{"id":"https://openalex.org/C67545415","wikidata":"https://www.wikidata.org/wiki/Q5384218","display_name":"Equalizer","level":3,"score":0.8003117442131042},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7733675241470337},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.6363599300384521},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.553964376449585},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5117921233177185},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.34042224287986755},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3104032278060913},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.2733207046985626},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.12400606274604797},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10085776448249817},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isscc.1984.1156673","doi":"https://doi.org/10.1109/isscc.1984.1156673","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isscc.1984.1156673","pdf_url":null,"source":{"id":"https://openalex.org/S4210210374","display_name":"Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference","issn_l":"0193-6530","issn":["0193-6530","2376-8606"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","norway-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2129732530","https://openalex.org/W2098062091","https://openalex.org/W2032069194","https://openalex.org/W2046928772","https://openalex.org/W2022223862","https://openalex.org/W2046718632","https://openalex.org/W3152098461","https://openalex.org/W2065827136","https://openalex.org/W2475485624","https://openalex.org/W2080584753"],"abstract_inverted_index":{"The":[0,21],"development":[1],"of":[2],"a":[3,24,27],"200Kb/s":[4],"digital":[5],"subscriber":[6],"loop":[7],"equalizer":[8],"using":[9],"an":[10],"analog-digital":[11],"standard":[12],"cell":[13],"building":[14],"block":[15],"design":[16],"system":[17],"will":[18],"be":[19],"described.":[20],"circuit":[22],"uses":[23],"2\u03bcm":[25],"CMOS,":[26],"single":[28],"5V":[29],"suoply,":[30],"and":[31,34],"includes":[32],"40dB\\sqrt{f}AGC":[33],"bridged":[35],"tap":[36],"equalizers.":[37]},"counts_by_year":[],"updated_date":"2026-10-14T16:39:01.820549","created_date":"2016-06-24T00:00:00"}