{"id":"https://openalex.org/W2017786130","doi":"https://doi.org/10.1109/paap.2014.51","title":"Bandwidth Based Performance Optimization of Multi-threaded Applications","display_name":"Bandwidth Based Performance Optimization of Multi-threaded Applications","publication_year":2014,"publication_date":"2014-07-01","ids":{"openalex":"https://openalex.org/W2017786130","doi":"https://doi.org/10.1109/paap.2014.51","mag":"2017786130"},"language":"en","primary_location":{"id":"doi:10.1109/paap.2014.51","doi":"https://doi.org/10.1109/paap.2014.51","is_oa":false,"landing_page_url":"https://doi.org/10.1109/paap.2014.51","pdf_url":null,"source":{"id":"https://openalex.org/S4306420191","display_name":"International Symposium on Parallel Architectures, Algorithms and Programming","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 Sixth International Symposium on Parallel Architectures, Algorithms and Programming","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5081633201","display_name":"Sheheeda Manakkadu","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I110378019","display_name":"Southern Illinois University Carbondale","ror":"https://ror.org/049kefs16","country_code":"US","type":"education","lineage":["https://openalex.org/I110378019","https://openalex.org/I2801502357"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sheheeda Manakkadu","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Southern Illinois University, Carbondale, Illinois","Dept. of Electr. & Comput. Eng., Southern Illinois Univ.-Carbondale, IL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Southern Illinois University, Carbondale, Illinois","institution_ids":["https://openalex.org/I110378019"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Southern Illinois Univ.-Carbondale, IL, USA","institution_ids":["https://openalex.org/I110378019"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5042216395","display_name":"Sourav Dutta","orcid":"https://orcid.org/0000-0002-8799-9237","observed_orcids":["https://orcid.org/0000-0002-8799-9237"]},"institutions":[{"id":"https://openalex.org/I110378019","display_name":"Southern Illinois University Carbondale","ror":"https://ror.org/049kefs16","country_code":"US","type":"education","lineage":["https://openalex.org/I110378019","https://openalex.org/I2801502357"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sourav Dutta","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Southern Illinois University, Carbondale, Illinois","Dept. of Electr. & Comput. Eng., Southern Illinois Univ.-Carbondale, IL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Southern Illinois University, Carbondale, Illinois","institution_ids":["https://openalex.org/I110378019"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Southern Illinois Univ.-Carbondale, IL, USA","institution_ids":["https://openalex.org/I110378019"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I110378019"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.0,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":88,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"118","last_page":"122"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":9.999999747378752e-05,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multithreaded-applications","display_name":"multithreaded programs","score":0.9470000267028809},{"id":"https://openalex.org/keywords/multi-core-processors","display_name":"multi-core processors","score":0.9319999814033508},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"memory bandwidth","score":0.9079999923706055},{"id":"https://openalex.org/keywords/scalability","display_name":"scalability","score":0.5350000262260437},{"id":"https://openalex.org/keywords/bandwidth-prediction","display_name":"bandwidth prediction","score":0.7049999833106995},{"id":"https://openalex.org/keywords/thread-synchronization","display_name":"thread synchronization","score":0.6570000052452087},{"id":"https://openalex.org/keywords/last-level-cache","display_name":"last-level cache","score":0.7889999747276306},{"id":"https://openalex.org/keywords/main-memory","display_name":"main memory","score":0.45899999141693115}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8659647703170776},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.6946015357971191},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.6899157762527466},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6710770130157471},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.6353512406349182},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.6347150802612305},{"id":"https://openalex.org/C2778476105","wikidata":"https://www.wikidata.org/wiki/Q628539","display_name":"Workload","level":2,"score":0.626230001449585},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6021961569786072},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.4886212944984436},{"id":"https://openalex.org/C201410400","wikidata":"https://www.wikidata.org/wiki/Q1064412","display_name":"Multithreading","level":3,"score":0.4789474606513977},{"id":"https://openalex.org/C2778915421","wikidata":"https://www.wikidata.org/wiki/Q3643177","display_name":"Performance improvement","level":2,"score":0.46833157539367676},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.37449488043785095},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.1951446235179901},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1572878658771515},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1325104832649231},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/paap.2014.51","doi":"https://doi.org/10.1109/paap.2014.51","is_oa":false,"landing_page_url":"https://doi.org/10.1109/paap.2014.51","pdf_url":null,"source":{"id":"https://openalex.org/S4306420191","display_name":"International Symposium on Parallel Architectures, Algorithms and Programming","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 Sixth International Symposium on Parallel Architectures, Algorithms and Programming","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1519939724","https://openalex.org/W1647880337","https://openalex.org/W1976229529","https://openalex.org/W1978418257","https://openalex.org/W2033424517","https://openalex.org/W2088257029","https://openalex.org/W2100913437","https://openalex.org/W2123892809","https://openalex.org/W2125623590","https://openalex.org/W2147657366","https://openalex.org/W2154702295","https://openalex.org/W4234144196","https://openalex.org/W4252854535","https://openalex.org/W4253029824"],"related_works":["https://openalex.org/W1965771437","https://openalex.org/W2755428707","https://openalex.org/W7096302695","https://openalex.org/W1555695963","https://openalex.org/W1185850368","https://openalex.org/W2125623590","https://openalex.org/W2067801022","https://openalex.org/W1539145441","https://openalex.org/W2134275560","https://openalex.org/W2165500483"],"abstract_inverted_index":{"Multiple":[0],"threads":[1,20,168],"running":[2],"on":[3,83,138],"a":[4,12,24,69,77,95,135,170],"multi-core":[5,84,148],"processor":[6],"can":[7,162],"improve":[8,36,106],"the":[9,66,88,102,107,124,132,151,156,164],"performance":[10,30,32,67,108,133],"of":[11,19,40,68,91,98,109,134,167],"parallel":[13,92,112,172],"application":[14],"significantly.":[15],"However,":[16],"effective":[17],"scaling":[18],"and":[21,58,86,122,150,174],"cores":[22],"plays":[23],"key":[25],"role":[26],"to":[27,46,79,105,130],"achieve":[28,80],"optimal":[29,81,165],"because":[31],"does":[33],"not":[34],"necessarily":[35],"with":[37],"increasing":[38],"number":[39,97,166],"cores.":[41],"Multi-threaded":[42],"applications":[43],"suffer":[44],"due":[45],"thread":[47],"synchronization,":[48],"negative":[49],"interference":[50],"in":[51],"shared":[52],"memory":[53],"including":[54],"last":[55],"level":[56],"cache":[57],"main":[59],"memory.":[60],"Memory":[61],"bandwidth":[62,89,110,126,159],"also":[63],"often":[64],"limits":[65],"multi-threaded":[70,139],"workload.":[71],"In":[72],"this":[73],"paper":[74],"we":[75],"propose":[76],"method":[78,104,145,161],"scalability":[82],"platform":[85],"predict":[87,131],"requirement":[90],"workloads":[93],"for":[94,169],"given":[96,136,171],"threads.":[99],"We":[100,114,141],"employ":[101],"proposed":[103,144],"limited":[111],"applications.":[113],"find":[115],"that":[116,155],"DRAM":[117],"access":[118],"has":[119,175],"various":[120],"phases":[121,129],"use":[123],"highest":[125],"among":[127],"all":[128],"workload":[137,173],"environment.":[140],"evaluate":[142],"our":[143],"using":[146],"Gem5":[147],"simulator":[149],"experimental":[152],"results":[153],"show":[154],"phase":[157],"based":[158],"utilization":[160],"estimate":[163],"low":[176],"prediction":[177],"error.":[178]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2019,"cited_by_count":1}],"updated_date":"2026-11-04T10:54:05.112534","created_date":"2016-06-24T00:00:00"}
